+2021-05-29 Mike Frysinger <vapier@gentoo.org>
+
+ * cache.h (frv_cache_unlock): New prototype.
+ * frv-sim.h (frvbf_media_average): Likewise.
+ (frv_queue_data_access_exception_interrupt): Likewise.
+ (frv_queue_division_exception_interrupt): Likewise.
+ (frvbf_check_acc_range): Likewise.
+ (frvbf_check_swap_address): Likewise.
+ (frvbf_*_multiple_*): Rename prototypes to ...
+ (frvbf_*_quad_*): ... these.
+ * profile-fr500.c (use_is_cc_complex): Put #if 0 around.
+ * profile-fr550.c (use_is_ccr_complex): Likewise.
+ * profile.h (frv_ref_SI): New prototype.
+ * registers.h (frv_check_spr_read_access): Likewise.
+ (frv_check_spr_write_access): Likewise.
+
2021-05-29 Mike Frysinger <vapier@gentoo.org>
* cache.c (non_cache_access): Add parentheses.
void frvbf_media_acc_not_aligned (SIM_CPU *);
void frvbf_media_cr_not_aligned (SIM_CPU *);
void frvbf_media_overflow (SIM_CPU *, int);
+SI frvbf_media_average (SIM_CPU *, SI, SI);
/* Functions for queuing and processing interrupts. */
struct frv_interrupt_queue_element *
struct frv_interrupt_queue_element *
frv_queue_data_access_error_interrupt (SIM_CPU *, USI);
+struct frv_interrupt_queue_element *
+frv_queue_data_access_exception_interrupt (SIM_CPU *);
+
struct frv_interrupt_queue_element *
frv_queue_instruction_access_error_interrupt (SIM_CPU *);
enum frv_dtt frvbf_division_exception (SIM_CPU *, enum frv_dtt, int, int);
+struct frv_interrupt_queue_element *
+frv_queue_division_exception_interrupt (SIM_CPU *, enum frv_dtt);
+
struct frv_interrupt_queue_element *
frv_queue_interrupt (SIM_CPU *, enum frv_interrupt_kind);
BI frvbf_check_non_excepting_load (SIM_CPU *, SI, SI, SI, SI, QI, BI);
void frvbf_check_recovering_store (SIM_CPU *, PCADDR, SI, int, int);
+SI frvbf_check_acc_range (SIM_CPU *, SI);
+void frvbf_check_swap_address (SIM_CPU *, SI);
void frvbf_clear_ne_flags (SIM_CPU *, SI, BI);
void frvbf_commit (SIM_CPU *, SI, BI);
#define INSNS_IN_SLOT(slot) (insns_in_slot[slot])
/* Multiple loads and stores. */
-void frvbf_load_multiple_GR (SIM_CPU *, PCADDR, SI, SI, int);
-void frvbf_load_multiple_FRint (SIM_CPU *, PCADDR, SI, SI, int);
-void frvbf_load_multiple_CPR (SIM_CPU *, PCADDR, SI, SI, int);
-void frvbf_store_multiple_GR (SIM_CPU *, PCADDR, SI, SI, int);
-void frvbf_store_multiple_FRint (SIM_CPU *, PCADDR, SI, SI, int);
-void frvbf_store_multiple_CPR (SIM_CPU *, PCADDR, SI, SI, int);
+void frvbf_load_quad_GR (SIM_CPU *, PCADDR, SI, SI);
+void frvbf_load_quad_FRint (SIM_CPU *, PCADDR, SI, SI);
+void frvbf_load_quad_CPR (SIM_CPU *, PCADDR, SI, SI);
+void frvbf_store_quad_GR (SIM_CPU *, PCADDR, SI, SI);
+void frvbf_store_quad_FRint (SIM_CPU *, PCADDR, SI, SI);
+void frvbf_store_quad_CPR (SIM_CPU *, PCADDR, SI, SI);
/* Memory and cache support. */
QI frvbf_read_mem_QI (SIM_CPU *, IADDR, SI);