build: always use platform.add_source and avoid manipulate platform.sources directly

diff --git a/litex/build/lattice/diamond.py b/litex/build/lattice/diamond.py
index a22288fd9a84de8fffb56e60dae9be154088c892..f4f06166b93c669d52c329639f72f4dc0b3c3b15 100644 (file)
--- a/litex/build/lattice/diamond.py
+++ b/litex/build/lattice/diamond.py
@@ -147,8 +147,8 @@ class LatticeDiamondToolchain:
         named_sc, named_pc = platform.resolve_signals(v_output.ns)
         v_file = build_name + ".v"
         v_output.write(v_file)
-        sources = platform.sources | {(v_file, "verilog", "work")}
-        _build_files(platform.device, sources, platform.verilog_include_paths, build_name)
+        platform.add_source(v_file)
+        _build_files(platform.device, platform.sources, platform.verilog_include_paths, build_name)
 
         tools.write_to_file(build_name + ".lpf", _build_lpf(named_sc, named_pc))
 

diff --git a/litex/build/lattice/icestorm.py b/litex/build/lattice/icestorm.py
index 20cabc952c02c2f0c01881fbcb6b68a2bfd186ea..0be9278fa8e33db2aa0969e708b5c372343a2486 100644 (file)
--- a/litex/build/lattice/icestorm.py
+++ b/litex/build/lattice/icestorm.py
@@ -137,13 +137,14 @@ class LatticeIceStormToolchain:
         named_sc, named_pc = platform.resolve_signals(v_output.ns)
         v_file = build_name + ".v"
         v_output.write(v_file)
+        platform.add_source(v_file)
 
         if use_nextpnr:
             chosen_yosys_template = self.nextpnr_yosys_template
         else:
             chosen_yosys_template = self.yosys_template
         ys_contents = "\n".join(_.format(build_name=build_name,
-                                         read_files=self.gen_read_files(platform, v_file),
+                                         read_files=self.gen_read_files(platform),
                                          synth_opts=synth_opts)
                                 for _ in chosen_yosys_template)
 
@@ -218,13 +219,12 @@ class LatticeIceStormToolchain:
     def get_size_string(self, series_size_str):
         return series_size_str[2:]
 
-    def gen_read_files(self, platform, main):
-        sources = platform.sources | {(main, "verilog", "work")}
+    def gen_read_files(self, platform):
         incflags = ""
         read_files = list()
         for path in platform.verilog_include_paths:
             incflags += " -I" + path
-        for filename, language, library in sources:
+        for filename, language, library in platform.sources:
             read_files.append("read_{}{} {}".format(language,
                                                     incflags,
                                                     filename))

diff --git a/litex/build/xilinx/ise.py b/litex/build/xilinx/ise.py
index 13f7488be51e68521399eda6da982554aa44580b..1d0e244a6f06cbf6464c0c4f46c4a9f6715afafd 100644 (file)
--- a/litex/build/xilinx/ise.py
+++ b/litex/build/xilinx/ise.py
@@ -202,12 +202,12 @@ class XilinxISEToolchain:
                 named_sc, named_pc = platform.resolve_signals(vns)
                 v_file = build_name + ".v"
                 v_output.write(v_file)
-                sources = platform.sources | {(v_file, "verilog", "work")}
+                platform.add_source(v_file)
                 if mode in ("xst", "cpld"):
-                    _build_xst_files(platform.device, sources, platform.verilog_include_paths, build_name, self.xst_opt)
+                    _build_xst_files(platform.device, platform.sources, platform.verilog_include_paths, build_name, self.xst_opt)
                     isemode = mode
                 else:
-                    _run_yosys(platform.device, sources, platform.verilog_include_paths, build_name)
+                    _run_yosys(platform.device, platform.sources, platform.verilog_include_paths, build_name)
                     isemode = "edif"
                     ngdbuild_opt += "-p " + platform.device
 

diff --git a/litex/build/xilinx/vivado.py b/litex/build/xilinx/vivado.py
index 9e307518047f42720c75bc5056c13aa8aa284d31..c64219924864d8bf09c75901b7e50d7a4d3ae761 100644 (file)
--- a/litex/build/xilinx/vivado.py
+++ b/litex/build/xilinx/vivado.py
@@ -253,7 +253,8 @@ class XilinxVivadoToolchain:
         named_sc, named_pc = platform.resolve_signals(v_output.ns)
         v_file = build_name + ".v"
         v_output.write(v_file)
-        sources = platform.sources | {(v_file, "verilog", "work")}
+        platform.add_source(v_file)
+        sources = platform.sources
         edifs = platform.edifs
         ips = platform.ips
         self._build_batch(platform, sources, edifs, ips, build_name, synth_mode, enable_xpm)