boards/platform/arty: add spiflash_4x/spiflash_1x to test SpiFlashDualQuad and SpiFla...

diff --git a/litex/boards/platforms/arty.py b/litex/boards/platforms/arty.py
index 0ed3f42037cb9e0d0f8de27949255eb5d2d3f271..d4c88eae1ee82c7d95d48c70901307ff79d097da 100644 (file)
--- a/litex/boards/platforms/arty.py
+++ b/litex/boards/platforms/arty.py
@@ -37,11 +37,19 @@ _io = [
         Subsignal("rx", Pins("A9")),
         IOStandard("LVCMOS33")),
 
-    ("spiflash", 0,  # clock needs to be accessed through STARTUPE2
+    ("spiflash_4x", 0,  # clock needs to be accessed through STARTUPE2
         Subsignal("cs_n", Pins("L13")),
         Subsignal("dq", Pins("K17", "K18", "L14", "M14")),
         IOStandard("LVCMOS33")
     ),
+    ("spiflash_1x", 0,  # clock needs to be accessed through STARTUPE2
+        Subsignal("cs_n", Pins("L13")),
+        Subsignal("mosi", Pins("K17")),
+        Subsignal("miso", Pins("K18")),
+        Subsignal("wp", Pins("L14")),
+        Subsignal("hold", Pins("M14")),
+        IOStandard("LVCMOS33")
+    ),
 
     ("eth_ref_clk", 0, Pins("G18"), IOStandard("LVCMOS33")),