mac: fix missing core csr generation

diff --git a/liteeth/mac/__init__.py b/liteeth/mac/__init__.py
index 5e88646bd1951de291c0351431a9d699166833fc..1517b7bd0d7b9621b4d92d37cd2093d577f21711 100644 (file)
--- a/liteeth/mac/__init__.py
+++ b/liteeth/mac/__init__.py
@@ -23,7 +23,7 @@ class LiteEthMAC(Module, AutoCSR):
                        self.submodules.interface = LiteEthMACWishboneInterface(dw, 2, 2)
                        self.comb += Port.connect(self.interface, self.core)
                        self.ev, self.bus = self.interface.sram.ev, self.interface.bus
-                       self.csrs = self.interface.get_csrs()
+                       self.csrs = self.interface.get_csrs() + self.core.get_csrs()
                elif interface == "dma":
                        raise NotImplementedError
                else: