fpga: Add support for Genesys2

Signed-off-by: Boris Shingarov <shingarov@labware.com>

diff --git a/fpga/genesys2.xdc b/fpga/genesys2.xdc
new file mode 100644 (file)
index 0000000..826e5f4
--- /dev/null
+++ b/fpga/genesys2.xdc
@@ -0,0 +1,463 @@
+#### Genesys-2 Rev.H
+
+## Clock & Reset
+set_property -dict { PACKAGE_PIN AD11  IOSTANDARD LVDS     } [get_ports { clk200_n }]
+set_property -dict { PACKAGE_PIN AD12  IOSTANDARD LVDS     } [get_ports { clk200_p }]
+create_clock -period 5.000 -name tc_clk100_p -waveform {0.000 2.500} [get_ports clk200_p]
+create_clock -period 5.000 -name tc_clk100_n -waveform {2.500 5.000} [get_ports clk200_n]
+
+set_property -dict { PACKAGE_PIN R19   IOSTANDARD LVCMOS33 } [get_ports { ext_rst }]
+
+## UART
+set_property -dict { PACKAGE_PIN Y20   IOSTANDARD LVCMOS33 } [get_ports { uart_main_rx }]
+set_property -dict { PACKAGE_PIN Y23   IOSTANDARD LVCMOS33 } [get_ports { uart_main_tx }]
+
+## LEDs
+set_property -dict { PACKAGE_PIN T28   IOSTANDARD LVCMOS33 } [get_ports { led0 }]
+set_property -dict { PACKAGE_PIN V19   IOSTANDARD LVCMOS33 } [get_ports { led1 }]
+set_property -dict { PACKAGE_PIN U30   IOSTANDARD LVCMOS33 } [get_ports { led2 }]
+set_property -dict { PACKAGE_PIN U29   IOSTANDARD LVCMOS33 } [get_ports { led3 }]
+
+## QSPI
+set_property -dict { PACKAGE_PIN U19   IOSTANDARD LVCMOS33 } [get_ports { spi_flash_cs_n   }]
+set_property -dict { PACKAGE_PIN P24   IOSTANDARD LVCMOS33 } [get_ports { spi_flash_mosi   }]
+set_property -dict { PACKAGE_PIN R25   IOSTANDARD LVCMOS33 } [get_ports { spi_flash_miso   }]
+set_property -dict { PACKAGE_PIN R20   IOSTANDARD LVCMOS33 } [get_ports { spi_flash_wp_n   }]
+set_property -dict { PACKAGE_PIN R21   IOSTANDARD LVCMOS33 } [get_ports { spi_flash_hold_n }]
+
+
+## DRAM
+
+# ddram:0.a
+set_property LOC AC12 [get_ports {ddram_a[0]}]
+set_property SLEW FAST [get_ports {ddram_a[0]}]
+set_property VCCAUX_IO HIGH [get_ports {ddram_a[0]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddram_a[0]}]
+
+# ddram:0.a
+set_property LOC AE8 [get_ports {ddram_a[1]}]
+set_property SLEW FAST [get_ports {ddram_a[1]}]
+set_property VCCAUX_IO HIGH [get_ports {ddram_a[1]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddram_a[1]}]
+
+# ddram:0.a
+set_property LOC AD8 [get_ports {ddram_a[2]}]
+set_property SLEW FAST [get_ports {ddram_a[2]}]
+set_property VCCAUX_IO HIGH [get_ports {ddram_a[2]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddram_a[2]}]
+
+# ddram:0.a
+set_property LOC AC10 [get_ports {ddram_a[3]}]
+set_property SLEW FAST [get_ports {ddram_a[3]}]
+set_property VCCAUX_IO HIGH [get_ports {ddram_a[3]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddram_a[3]}]
+
+# ddram:0.a
+set_property LOC AD9 [get_ports {ddram_a[4]}]
+set_property SLEW FAST [get_ports {ddram_a[4]}]
+set_property VCCAUX_IO HIGH [get_ports {ddram_a[4]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddram_a[4]}]
+
+# ddram:0.a
+set_property LOC AA13 [get_ports {ddram_a[5]}]
+set_property SLEW FAST [get_ports {ddram_a[5]}]
+set_property VCCAUX_IO HIGH [get_ports {ddram_a[5]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddram_a[5]}]
+
+# ddram:0.a
+set_property LOC AA10 [get_ports {ddram_a[6]}]
+set_property SLEW FAST [get_ports {ddram_a[6]}]
+set_property VCCAUX_IO HIGH [get_ports {ddram_a[6]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddram_a[6]}]
+
+# ddram:0.a
+set_property LOC AA11 [get_ports {ddram_a[7]}]
+set_property SLEW FAST [get_ports {ddram_a[7]}]
+set_property VCCAUX_IO HIGH [get_ports {ddram_a[7]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddram_a[7]}]
+
+# ddram:0.a
+set_property LOC Y10 [get_ports {ddram_a[8]}]
+set_property SLEW FAST [get_ports {ddram_a[8]}]
+set_property VCCAUX_IO HIGH [get_ports {ddram_a[8]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddram_a[8]}]
+
+# ddram:0.a
+set_property LOC Y11 [get_ports {ddram_a[9]}]
+set_property SLEW FAST [get_ports {ddram_a[9]}]
+set_property VCCAUX_IO HIGH [get_ports {ddram_a[9]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddram_a[9]}]
+
+# ddram:0.a
+set_property LOC AB8 [get_ports {ddram_a[10]}]
+set_property SLEW FAST [get_ports {ddram_a[10]}]
+set_property VCCAUX_IO HIGH [get_ports {ddram_a[10]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddram_a[10]}]
+
+# ddram:0.a
+set_property LOC AA8 [get_ports {ddram_a[11]}]
+set_property SLEW FAST [get_ports {ddram_a[11]}]
+set_property VCCAUX_IO HIGH [get_ports {ddram_a[11]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddram_a[11]}]
+
+# ddram:0.a
+set_property LOC AB12 [get_ports {ddram_a[12]}]
+set_property SLEW FAST [get_ports {ddram_a[12]}]
+set_property VCCAUX_IO HIGH [get_ports {ddram_a[12]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddram_a[12]}]
+
+# ddram:0.a
+set_property LOC AA12 [get_ports {ddram_a[13]}]
+set_property SLEW FAST [get_ports {ddram_a[13]}]
+set_property VCCAUX_IO HIGH [get_ports {ddram_a[13]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddram_a[13]}]
+
+# ddram:0.a
+set_property LOC AH9 [get_ports {ddram_a[14]}]
+set_property SLEW FAST [get_ports {ddram_a[14]}]
+set_property VCCAUX_IO HIGH [get_ports {ddram_a[14]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddram_a[14]}]
+
+# ddram:0.ba
+set_property LOC AE9 [get_ports {ddram_ba[0]}]
+set_property SLEW FAST [get_ports {ddram_ba[0]}]
+set_property VCCAUX_IO HIGH [get_ports {ddram_ba[0]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddram_ba[0]}]
+
+# ddram:0.ba
+set_property LOC AB10 [get_ports {ddram_ba[1]}]
+set_property SLEW FAST [get_ports {ddram_ba[1]}]
+set_property VCCAUX_IO HIGH [get_ports {ddram_ba[1]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddram_ba[1]}]
+
+# ddram:0.ba
+set_property LOC AC11 [get_ports {ddram_ba[2]}]
+set_property SLEW FAST [get_ports {ddram_ba[2]}]
+set_property VCCAUX_IO HIGH [get_ports {ddram_ba[2]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddram_ba[2]}]
+
+# ddram:0.ras_n
+set_property LOC AE11 [get_ports {ddram_ras_n}]
+set_property SLEW FAST [get_ports {ddram_ras_n}]
+set_property VCCAUX_IO HIGH [get_ports {ddram_ras_n}]
+set_property IOSTANDARD SSTL15 [get_ports {ddram_ras_n}]
+
+# ddram:0.cas_n
+set_property LOC AF11 [get_ports {ddram_cas_n}]
+set_property SLEW FAST [get_ports {ddram_cas_n}]
+set_property VCCAUX_IO HIGH [get_ports {ddram_cas_n}]
+set_property IOSTANDARD SSTL15 [get_ports {ddram_cas_n}]
+
+# ddram:0.we_n
+set_property LOC AG13 [get_ports {ddram_we_n}]
+set_property SLEW FAST [get_ports {ddram_we_n}]
+set_property VCCAUX_IO HIGH [get_ports {ddram_we_n}]
+set_property IOSTANDARD SSTL15 [get_ports {ddram_we_n}]
+
+# ddram:0.cs_n
+set_property LOC AH12 [get_ports {ddram_cs_n}]
+set_property SLEW FAST [get_ports {ddram_cs_n}]
+set_property VCCAUX_IO HIGH [get_ports {ddram_cs_n}]
+set_property IOSTANDARD SSTL15 [get_ports {ddram_cs_n}]
+
+# ddram:0.dm
+set_property LOC AD4 [get_ports {ddram_dm[0]}]
+set_property SLEW FAST [get_ports {ddram_dm[0]}]
+set_property VCCAUX_IO HIGH [get_ports {ddram_dm[0]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddram_dm[0]}]
+
+# ddram:0.dm
+set_property LOC AF3 [get_ports {ddram_dm[1]}]
+set_property SLEW FAST [get_ports {ddram_dm[1]}]
+set_property VCCAUX_IO HIGH [get_ports {ddram_dm[1]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddram_dm[1]}]
+
+# ddram:0.dm
+set_property LOC AH4 [get_ports {ddram_dm[2]}]
+set_property SLEW FAST [get_ports {ddram_dm[2]}]
+set_property VCCAUX_IO HIGH [get_ports {ddram_dm[2]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddram_dm[2]}]
+
+# ddram:0.dm
+set_property LOC AF8 [get_ports {ddram_dm[3]}]
+set_property SLEW FAST [get_ports {ddram_dm[3]}]
+set_property VCCAUX_IO HIGH [get_ports {ddram_dm[3]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddram_dm[3]}]
+
+# ddram:0.dq
+set_property LOC AD3 [get_ports {ddram_dq[0]}]
+set_property SLEW FAST [get_ports {ddram_dq[0]}]
+set_property VCCAUX_IO HIGH [get_ports {ddram_dq[0]}]
+set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddram_dq[0]}]
+
+# ddram:0.dq
+set_property LOC AC2 [get_ports {ddram_dq[1]}]
+set_property SLEW FAST [get_ports {ddram_dq[1]}]
+set_property VCCAUX_IO HIGH [get_ports {ddram_dq[1]}]
+set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddram_dq[1]}]
+
+# ddram:0.dq
+set_property LOC AC1 [get_ports {ddram_dq[2]}]
+set_property SLEW FAST [get_ports {ddram_dq[2]}]
+set_property VCCAUX_IO HIGH [get_ports {ddram_dq[2]}]
+set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddram_dq[2]}]
+
+# ddram:0.dq
+set_property LOC AC5 [get_ports {ddram_dq[3]}]
+set_property SLEW FAST [get_ports {ddram_dq[3]}]
+set_property VCCAUX_IO HIGH [get_ports {ddram_dq[3]}]
+set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddram_dq[3]}]
+
+# ddram:0.dq
+set_property LOC AC4 [get_ports {ddram_dq[4]}]
+set_property SLEW FAST [get_ports {ddram_dq[4]}]
+set_property VCCAUX_IO HIGH [get_ports {ddram_dq[4]}]
+set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddram_dq[4]}]
+
+# ddram:0.dq
+set_property LOC AD6 [get_ports {ddram_dq[5]}]
+set_property SLEW FAST [get_ports {ddram_dq[5]}]
+set_property VCCAUX_IO HIGH [get_ports {ddram_dq[5]}]
+set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddram_dq[5]}]
+
+# ddram:0.dq
+set_property LOC AE6 [get_ports {ddram_dq[6]}]
+set_property SLEW FAST [get_ports {ddram_dq[6]}]
+set_property VCCAUX_IO HIGH [get_ports {ddram_dq[6]}]
+set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddram_dq[6]}]
+
+# ddram:0.dq
+set_property LOC AC7 [get_ports {ddram_dq[7]}]
+set_property SLEW FAST [get_ports {ddram_dq[7]}]
+set_property VCCAUX_IO HIGH [get_ports {ddram_dq[7]}]
+set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddram_dq[7]}]
+
+# ddram:0.dq
+set_property LOC AF2 [get_ports {ddram_dq[8]}]
+set_property SLEW FAST [get_ports {ddram_dq[8]}]
+set_property VCCAUX_IO HIGH [get_ports {ddram_dq[8]}]
+set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddram_dq[8]}]
+
+# ddram:0.dq
+set_property LOC AE1 [get_ports {ddram_dq[9]}]
+set_property SLEW FAST [get_ports {ddram_dq[9]}]
+set_property VCCAUX_IO HIGH [get_ports {ddram_dq[9]}]
+set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddram_dq[9]}]
+
+# ddram:0.dq
+set_property LOC AF1 [get_ports {ddram_dq[10]}]
+set_property SLEW FAST [get_ports {ddram_dq[10]}]
+set_property VCCAUX_IO HIGH [get_ports {ddram_dq[10]}]
+set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddram_dq[10]}]
+
+# ddram:0.dq
+set_property LOC AE4 [get_ports {ddram_dq[11]}]
+set_property SLEW FAST [get_ports {ddram_dq[11]}]
+set_property VCCAUX_IO HIGH [get_ports {ddram_dq[11]}]
+set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddram_dq[11]}]
+
+# ddram:0.dq
+set_property LOC AE3 [get_ports {ddram_dq[12]}]
+set_property SLEW FAST [get_ports {ddram_dq[12]}]
+set_property VCCAUX_IO HIGH [get_ports {ddram_dq[12]}]
+set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddram_dq[12]}]
+
+# ddram:0.dq
+set_property LOC AE5 [get_ports {ddram_dq[13]}]
+set_property SLEW FAST [get_ports {ddram_dq[13]}]
+set_property VCCAUX_IO HIGH [get_ports {ddram_dq[13]}]
+set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddram_dq[13]}]
+
+# ddram:0.dq
+set_property LOC AF5 [get_ports {ddram_dq[14]}]
+set_property SLEW FAST [get_ports {ddram_dq[14]}]
+set_property VCCAUX_IO HIGH [get_ports {ddram_dq[14]}]
+set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddram_dq[14]}]
+
+# ddram:0.dq
+set_property LOC AF6 [get_ports {ddram_dq[15]}]
+set_property SLEW FAST [get_ports {ddram_dq[15]}]
+set_property VCCAUX_IO HIGH [get_ports {ddram_dq[15]}]
+set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddram_dq[15]}]
+
+# ddram:0.dq
+set_property LOC AJ4 [get_ports {ddram_dq[16]}]
+set_property SLEW FAST [get_ports {ddram_dq[16]}]
+set_property VCCAUX_IO HIGH [get_ports {ddram_dq[16]}]
+set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddram_dq[16]}]
+
+# ddram:0.dq
+set_property LOC AH6 [get_ports {ddram_dq[17]}]
+set_property SLEW FAST [get_ports {ddram_dq[17]}]
+set_property VCCAUX_IO HIGH [get_ports {ddram_dq[17]}]
+set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddram_dq[17]}]
+
+# ddram:0.dq
+set_property LOC AH5 [get_ports {ddram_dq[18]}]
+set_property SLEW FAST [get_ports {ddram_dq[18]}]
+set_property VCCAUX_IO HIGH [get_ports {ddram_dq[18]}]
+set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddram_dq[18]}]
+
+# ddram:0.dq
+set_property LOC AH2 [get_ports {ddram_dq[19]}]
+set_property SLEW FAST [get_ports {ddram_dq[19]}]
+set_property VCCAUX_IO HIGH [get_ports {ddram_dq[19]}]
+set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddram_dq[19]}]
+
+# ddram:0.dq
+set_property LOC AJ2 [get_ports {ddram_dq[20]}]
+set_property SLEW FAST [get_ports {ddram_dq[20]}]
+set_property VCCAUX_IO HIGH [get_ports {ddram_dq[20]}]
+set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddram_dq[20]}]
+
+# ddram:0.dq
+set_property LOC AJ1 [get_ports {ddram_dq[21]}]
+set_property SLEW FAST [get_ports {ddram_dq[21]}]
+set_property VCCAUX_IO HIGH [get_ports {ddram_dq[21]}]
+set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddram_dq[21]}]
+
+# ddram:0.dq
+set_property LOC AK1 [get_ports {ddram_dq[22]}]
+set_property SLEW FAST [get_ports {ddram_dq[22]}]
+set_property VCCAUX_IO HIGH [get_ports {ddram_dq[22]}]
+set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddram_dq[22]}]
+
+# ddram:0.dq
+set_property LOC AJ3 [get_ports {ddram_dq[23]}]
+set_property SLEW FAST [get_ports {ddram_dq[23]}]
+set_property VCCAUX_IO HIGH [get_ports {ddram_dq[23]}]
+set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddram_dq[23]}]
+
+# ddram:0.dq
+set_property LOC AF7 [get_ports {ddram_dq[24]}]
+set_property SLEW FAST [get_ports {ddram_dq[24]}]
+set_property VCCAUX_IO HIGH [get_ports {ddram_dq[24]}]
+set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddram_dq[24]}]
+
+# ddram:0.dq
+set_property LOC AG7 [get_ports {ddram_dq[25]}]
+set_property SLEW FAST [get_ports {ddram_dq[25]}]
+set_property VCCAUX_IO HIGH [get_ports {ddram_dq[25]}]
+set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddram_dq[25]}]
+
+# ddram:0.dq
+set_property LOC AJ6 [get_ports {ddram_dq[26]}]
+set_property SLEW FAST [get_ports {ddram_dq[26]}]
+set_property VCCAUX_IO HIGH [get_ports {ddram_dq[26]}]
+set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddram_dq[26]}]
+
+# ddram:0.dq
+set_property LOC AK6 [get_ports {ddram_dq[27]}]
+set_property SLEW FAST [get_ports {ddram_dq[27]}]
+set_property VCCAUX_IO HIGH [get_ports {ddram_dq[27]}]
+set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddram_dq[27]}]
+
+# ddram:0.dq
+set_property LOC AJ8 [get_ports {ddram_dq[28]}]
+set_property SLEW FAST [get_ports {ddram_dq[28]}]
+set_property VCCAUX_IO HIGH [get_ports {ddram_dq[28]}]
+set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddram_dq[28]}]
+
+# ddram:0.dq
+set_property LOC AK8 [get_ports {ddram_dq[29]}]
+set_property SLEW FAST [get_ports {ddram_dq[29]}]
+set_property VCCAUX_IO HIGH [get_ports {ddram_dq[29]}]
+set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddram_dq[29]}]
+
+# ddram:0.dq
+set_property LOC AK5 [get_ports {ddram_dq[30]}]
+set_property SLEW FAST [get_ports {ddram_dq[30]}]
+set_property VCCAUX_IO HIGH [get_ports {ddram_dq[30]}]
+set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddram_dq[30]}]
+
+# ddram:0.dq
+set_property LOC AK4 [get_ports {ddram_dq[31]}]
+set_property SLEW FAST [get_ports {ddram_dq[31]}]
+set_property VCCAUX_IO HIGH [get_ports {ddram_dq[31]}]
+set_property IOSTANDARD SSTL15_T_DCI [get_ports {ddram_dq[31]}]
+
+# ddram:0.dqs_p
+set_property LOC AD2 [get_ports {ddram_dqs_p[0]}]
+set_property SLEW FAST [get_ports {ddram_dqs_p[0]}]
+set_property VCCAUX_IO HIGH [get_ports {ddram_dqs_p[0]}]
+set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddram_dqs_p[0]}]
+
+# ddram:0.dqs_p
+set_property LOC AG4 [get_ports {ddram_dqs_p[1]}]
+set_property SLEW FAST [get_ports {ddram_dqs_p[1]}]
+set_property VCCAUX_IO HIGH [get_ports {ddram_dqs_p[1]}]
+set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddram_dqs_p[1]}]
+
+# ddram:0.dqs_p
+set_property LOC AG2 [get_ports {ddram_dqs_p[2]}]
+set_property SLEW FAST [get_ports {ddram_dqs_p[2]}]
+set_property VCCAUX_IO HIGH [get_ports {ddram_dqs_p[2]}]
+set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddram_dqs_p[2]}]
+
+# ddram:0.dqs_p
+set_property LOC AH7 [get_ports {ddram_dqs_p[3]}]
+set_property SLEW FAST [get_ports {ddram_dqs_p[3]}]
+set_property VCCAUX_IO HIGH [get_ports {ddram_dqs_p[3]}]
+set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddram_dqs_p[3]}]
+
+# ddram:0.dqs_n
+set_property LOC AD1 [get_ports {ddram_dqs_n[0]}]
+set_property SLEW FAST [get_ports {ddram_dqs_n[0]}]
+set_property VCCAUX_IO HIGH [get_ports {ddram_dqs_n[0]}]
+set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddram_dqs_n[0]}]
+
+# ddram:0.dqs_n
+set_property LOC AG3 [get_ports {ddram_dqs_n[1]}]
+set_property SLEW FAST [get_ports {ddram_dqs_n[1]}]
+set_property VCCAUX_IO HIGH [get_ports {ddram_dqs_n[1]}]
+set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddram_dqs_n[1]}]
+
+# ddram:0.dqs_n
+set_property LOC AH1 [get_ports {ddram_dqs_n[2]}]
+set_property SLEW FAST [get_ports {ddram_dqs_n[2]}]
+set_property VCCAUX_IO HIGH [get_ports {ddram_dqs_n[2]}]
+set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddram_dqs_n[2]}]
+
+# ddram:0.dqs_n
+set_property LOC AJ7 [get_ports {ddram_dqs_n[3]}]
+set_property SLEW FAST [get_ports {ddram_dqs_n[3]}]
+set_property VCCAUX_IO HIGH [get_ports {ddram_dqs_n[3]}]
+set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddram_dqs_n[3]}]
+
+# ddram:0.clk_p
+set_property LOC AB9 [get_ports {ddram_clk_p}]
+set_property SLEW FAST [get_ports {ddram_clk_p}]
+set_property VCCAUX_IO HIGH [get_ports {ddram_clk_p}]
+set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddram_clk_p}]
+
+# ddram:0.clk_n
+set_property LOC AC9 [get_ports {ddram_clk_n}]
+set_property SLEW FAST [get_ports {ddram_clk_n}]
+set_property VCCAUX_IO HIGH [get_ports {ddram_clk_n}]
+set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddram_clk_n}]
+
+# ddram:0.cke
+set_property LOC AJ9 [get_ports {ddram_cke}]
+set_property SLEW FAST [get_ports {ddram_cke}]
+set_property VCCAUX_IO HIGH [get_ports {ddram_cke}]
+set_property IOSTANDARD SSTL15 [get_ports {ddram_cke}]
+
+# ddram:0.odt
+set_property LOC AK9 [get_ports {ddram_odt}]
+set_property SLEW FAST [get_ports {ddram_odt}]
+set_property VCCAUX_IO HIGH [get_ports {ddram_odt}]
+set_property IOSTANDARD SSTL15 [get_ports {ddram_odt}]
+
+# ddram:0.reset_n
+set_property LOC AG5 [get_ports {ddram_reset_n}]
+set_property SLEW FAST [get_ports {ddram_reset_n}]
+set_property VCCAUX_IO HIGH [get_ports {ddram_reset_n}]
+set_property IOSTANDARD LVCMOS15 [get_ports {ddram_reset_n}]
+
+
+set_property INTERNAL_VREF 0.750 [get_iobanks 34]
+
+# False path constraints
+set_false_path -quiet -through [get_nets -hierarchical -filter {mr_ff == TRUE}]
+set_false_path -quiet -to [get_pins -filter {REF_PIN_NAME == PRE} -of_objects [get_cells -hierarchical -filter {ars_ff1 == TRUE || ars_ff2 == TRUE}]]
+set_max_delay 2 -quiet -from [get_pins -filter {REF_PIN_NAME == C} -of_objects [get_cells -hierarchical -filter {ars_ff1 == TRUE}]] -to [get_pins -filter {REF_PIN_NAME == D} -of_objects [get_cells -hierarchical -filter {ars_ff2 == TRUE}]]

diff --git a/fpga/top-genesys2.vhdl b/fpga/top-genesys2.vhdl
new file mode 100644 (file)
index 0000000..fcd190f
--- /dev/null
+++ b/fpga/top-genesys2.vhdl
@@ -0,0 +1,322 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library unisim;
+use unisim.vcomponents.all;
+
+library work;
+use work.wishbone_types.all;
+
+entity toplevel is
+    generic (
+       MEMORY_SIZE   : integer := 16384;
+       RAM_INIT_FILE : string   := "firmware.hex";
+       RESET_LOW     : boolean  := true;
+       CLK_FREQUENCY : positive := 100000000;
+       USE_LITEDRAM  : boolean  := false;
+       NO_BRAM       : boolean  := false;
+       DISABLE_FLATTEN_CORE : boolean := false;
+        SPI_FLASH_OFFSET   : integer := 10485760;
+        SPI_FLASH_DEF_CKDV : natural := 1;
+        SPI_FLASH_DEF_QUAD : boolean := true;
+        LOG_LENGTH         : natural := 2048;
+        UART_IS_16550      : boolean := true
+       );
+    port(
+       clk200_p   : in  std_ulogic;
+       clk200_n   : in  std_ulogic;
+       ext_rst    : in  std_ulogic;
+
+       -- UART0 signals:
+       uart_main_tx : out std_ulogic;
+       uart_main_rx : in  std_ulogic;
+
+       -- LEDs
+       led0    : out std_logic;
+       led1    : out std_logic;
+       led2    : out std_logic;
+       led3    : out std_logic;
+
+        -- SPI
+        spi_flash_cs_n   : out std_ulogic;
+        spi_flash_mosi   : inout std_ulogic;
+        spi_flash_miso   : inout std_ulogic;
+        spi_flash_wp_n   : inout std_ulogic;
+        spi_flash_hold_n : inout std_ulogic;
+
+       -- DRAM wires
+       ddram_a       : out std_logic_vector(14 downto 0);
+       ddram_ba      : out std_logic_vector(2 downto 0);
+       ddram_ras_n   : out std_logic;
+       ddram_cas_n   : out std_logic;
+       ddram_we_n    : out std_logic;
+       ddram_cs_n    : out std_ulogic;
+       ddram_dm      : out std_logic_vector(3 downto 0);
+       ddram_dq      : inout std_logic_vector(31 downto 0);
+       ddram_dqs_p   : inout std_logic_vector(3 downto 0);
+       ddram_dqs_n   : inout std_logic_vector(3 downto 0);
+       ddram_clk_p   : out std_logic;
+       ddram_clk_n   : out std_logic;
+       ddram_cke     : out std_logic;
+       ddram_odt     : out std_logic;
+       ddram_reset_n : out std_logic
+       );
+end entity toplevel;
+
+architecture behaviour of toplevel is
+
+    -- Internal clock
+    signal ext_clk : std_ulogic;
+
+    -- Reset signals:
+    signal soc_rst : std_ulogic;
+    signal pll_rst : std_ulogic;
+
+    -- Internal clock signals:
+    signal system_clk : std_ulogic;
+    signal system_clk_locked : std_ulogic;
+
+    -- DRAM main data wishbone connection
+    signal wb_dram_in       : wishbone_master_out;
+    signal wb_dram_out      : wishbone_slave_out;
+
+    -- DRAM control wishbone connection
+    signal wb_ext_io_in        : wb_io_master_out;
+    signal wb_ext_io_out       : wb_io_slave_out;
+    signal wb_ext_is_dram_csr  : std_ulogic;
+    signal wb_ext_is_dram_init : std_ulogic;
+
+    -- Control/status
+    signal core_alt_reset : std_ulogic;
+
+    -- SPI flash
+    signal spi_sck     : std_ulogic;
+    signal spi_cs_n    : std_ulogic;
+    signal spi_sdat_o  : std_ulogic_vector(3 downto 0);
+    signal spi_sdat_oe : std_ulogic_vector(3 downto 0);
+    signal spi_sdat_i  : std_ulogic_vector(3 downto 0);
+
+    -- Fixup various memory sizes based on generics
+    function get_bram_size return natural is
+    begin
+        if USE_LITEDRAM and NO_BRAM then
+            return 0;
+        else
+            return MEMORY_SIZE;
+        end if;
+    end function;
+
+    function get_payload_size return natural is
+    begin
+        if USE_LITEDRAM and NO_BRAM then
+            return MEMORY_SIZE;
+        else
+            return 0;
+        end if;
+    end function;
+
+    constant BRAM_SIZE    : natural := get_bram_size;
+    constant PAYLOAD_SIZE : natural := get_payload_size;
+begin
+
+    -- Main SoC
+    soc0: entity work.soc
+       generic map(
+           MEMORY_SIZE   => BRAM_SIZE,
+           RAM_INIT_FILE => RAM_INIT_FILE,
+           SIM           => false,
+           CLK_FREQ      => CLK_FREQUENCY,
+           HAS_DRAM      => USE_LITEDRAM,
+           DRAM_SIZE     => 1024 * 1024 * 1024,
+            DRAM_INIT_SIZE => PAYLOAD_SIZE,
+           DISABLE_FLATTEN_CORE => DISABLE_FLATTEN_CORE,
+            HAS_SPI_FLASH      => true,
+            SPI_FLASH_DLINES   => 4,
+            SPI_FLASH_OFFSET   => SPI_FLASH_OFFSET,
+            SPI_FLASH_DEF_CKDV => SPI_FLASH_DEF_CKDV,
+            SPI_FLASH_DEF_QUAD => SPI_FLASH_DEF_QUAD,
+            LOG_LENGTH         => LOG_LENGTH,
+            UART0_IS_16550     => UART_IS_16550
+           )
+       port map (
+            -- System signals
+           system_clk        => system_clk,
+           rst               => soc_rst,
+
+            -- UART signals
+            uart0_txd         => uart_main_tx,
+           uart0_rxd         => uart_main_rx,
+
+            -- SPI signals
+            spi_flash_sck     => spi_sck,
+            spi_flash_cs_n    => spi_cs_n,
+            spi_flash_sdat_o  => spi_sdat_o,
+            spi_flash_sdat_oe => spi_sdat_oe,
+            spi_flash_sdat_i  => spi_sdat_i,
+
+            -- DRAM wishbone
+           wb_dram_in          => wb_dram_in,
+           wb_dram_out         => wb_dram_out,
+           wb_ext_io_in        => wb_ext_io_in,
+           wb_ext_io_out       => wb_ext_io_out,
+           wb_ext_is_dram_csr  => wb_ext_is_dram_csr,
+           wb_ext_is_dram_init => wb_ext_is_dram_init,
+           alt_reset           => core_alt_reset
+           );
+
+    -- SPI Flash. The SPI clk needs to be fed through the STARTUPE2
+    -- primitive of the FPGA as it's not a normal pin
+    --
+    spi_flash_cs_n   <= spi_cs_n;
+    spi_flash_mosi   <= spi_sdat_o(0) when spi_sdat_oe(0) = '1' else 'Z';
+    spi_flash_miso   <= spi_sdat_o(1) when spi_sdat_oe(1) = '1' else 'Z';
+    spi_flash_wp_n   <= spi_sdat_o(2) when spi_sdat_oe(2) = '1' else 'Z';
+    spi_flash_hold_n <= spi_sdat_o(3) when spi_sdat_oe(3) = '1' else 'Z';
+    spi_sdat_i(0)    <= spi_flash_mosi;
+    spi_sdat_i(1)    <= spi_flash_miso;
+    spi_sdat_i(2)    <= spi_flash_wp_n;
+    spi_sdat_i(3)    <= spi_flash_hold_n;
+
+    STARTUPE2_INST: STARTUPE2
+        port map (
+            CLK => '0',
+            GSR => '0',
+            GTS => '0',
+            KEYCLEARB => '0',
+            PACK => '0',
+            USRCCLKO => spi_sck,
+            USRCCLKTS => '0',
+            USRDONEO => '1',
+            USRDONETS => '0'
+            );
+
+    clk200: IBUFDS
+        port map (
+            i  => clk200_p,
+            ib => clk200_n,
+            o  => ext_clk
+        );
+
+    nodram: if not USE_LITEDRAM generate
+        signal ddram_clk_dummy : std_ulogic;
+    begin
+       reset_controller: entity work.soc_reset
+           generic map(
+               RESET_LOW => RESET_LOW
+               )
+           port map(
+               ext_clk => ext_clk,
+               pll_clk => system_clk,
+               pll_locked_in => system_clk_locked,
+               ext_rst_in => ext_rst,
+               pll_rst_out => pll_rst,
+               rst_out => soc_rst
+               );
+
+       clkgen: entity work.clock_generator
+           generic map(
+               CLK_INPUT_HZ => 200000000,
+               CLK_OUTPUT_HZ => CLK_FREQUENCY
+               )
+           port map(
+               ext_clk => ext_clk,
+               pll_rst_in => pll_rst,
+               pll_clk_out => system_clk,
+               pll_locked_out => system_clk_locked
+               );
+
+       led0 <= soc_rst;
+       led1 <= pll_rst;
+        led2 <= not system_clk_locked;
+       led3 <= '0';
+       core_alt_reset <= '0';
+
+        -- Vivado barfs on those differential signals if left
+        -- unconnected. So instanciate a diff. buffer and feed
+        -- it a constant '0'.
+        dummy_dram_clk: OBUFDS
+            port map (
+                O => ddram_clk_p,
+                OB => ddram_clk_n,
+                I => ddram_clk_dummy
+                );
+        ddram_clk_dummy <= '0';
+
+    end generate;
+
+    has_dram: if USE_LITEDRAM generate
+       signal dram_init_done  : std_ulogic;
+       signal dram_init_error : std_ulogic;
+       signal dram_sys_rst    : std_ulogic;
+    begin
+
+       -- Eventually dig out the frequency from the generator
+       -- but for now, assert it's 100Mhz
+       assert CLK_FREQUENCY = 100000000;
+
+       reset_controller: entity work.soc_reset
+           generic map(
+               RESET_LOW => RESET_LOW,
+                PLL_RESET_BITS => 18,
+                SOC_RESET_BITS => 1
+               )
+           port map(
+               ext_clk => ext_clk,
+               pll_clk => system_clk,
+               pll_locked_in => '1',
+               ext_rst_in => ext_rst,
+               pll_rst_out => pll_rst,
+               rst_out => open
+               );
+
+       dram: entity work.litedram_wrapper
+           generic map(
+               DRAM_ABITS => 25,
+               DRAM_ALINES => 15,
+                DRAM_DLINES => 32,
+                DRAM_PORT_WIDTH => 256,
+                PAYLOAD_FILE => RAM_INIT_FILE,
+                PAYLOAD_SIZE => PAYLOAD_SIZE
+               )
+           port map(
+               clk_in          => ext_clk,
+               rst             => pll_rst,
+               system_clk      => system_clk,
+               system_reset    => soc_rst,
+                core_alt_reset  => core_alt_reset,
+               pll_locked      => system_clk_locked,
+
+               wb_in           => wb_dram_in,
+               wb_out          => wb_dram_out,
+               wb_ctrl_in      => wb_ext_io_in,
+               wb_ctrl_out     => wb_ext_io_out,
+               wb_ctrl_is_csr  => wb_ext_is_dram_csr,
+               wb_ctrl_is_init => wb_ext_is_dram_init,
+
+               init_done       => dram_init_done,
+               init_error      => dram_init_error,
+
+               ddram_a         => ddram_a,
+               ddram_ba        => ddram_ba,
+               ddram_ras_n     => ddram_ras_n,
+               ddram_cas_n     => ddram_cas_n,
+               ddram_we_n      => ddram_we_n,
+               ddram_cs_n      => ddram_cs_n,
+               ddram_dm        => ddram_dm,
+               ddram_dq        => ddram_dq,
+               ddram_dqs_p     => ddram_dqs_p,
+               ddram_dqs_n     => ddram_dqs_n,
+               ddram_clk_p     => ddram_clk_p,
+               ddram_clk_n     => ddram_clk_n,
+               ddram_cke       => ddram_cke,
+               ddram_odt       => ddram_odt,
+               ddram_reset_n   => ddram_reset_n
+               );
+
+        led0 <= soc_rst;
+       led1 <= pll_rst;
+       led2 <= not dram_init_done or dram_init_error;
+       led3 <= not dram_init_error; -- Make it blink ?
+    end generate;
+end architecture behaviour;

diff --git a/litedram/gen-src/genesys2.yml b/litedram/gen-src/genesys2.yml
index 9f2108b6dc25da3b18a0f82c542d3d0014dc6d4c..6cf8ac1e6d03ca9727116b0cd0928ae4c0ee81a8 100644 (file)
--- a/litedram/gen-src/genesys2.yml
+++ b/litedram/gen-src/genesys2.yml
@@ -9,7 +9,7 @@
     "memtype":    "DDR3",      # DRAM type
 
     # PHY ----------------------------------------------------------------------
-    "cmd_latency":     0,             # Command additional latency
+    "cmd_latency":     1,             # Command additional latency
     "sdram_module":    "MT41J256M16", # SDRAM modules of the board or SO-DIMM
     "sdram_module_nb": 4,             # Number of byte groups
     "sdram_rank_nb":   1,             # Number of ranks

diff --git a/litedram/generated/genesys2/litedram_core.v b/litedram/generated/genesys2/litedram_core.v
index a0f6e8a176c1c8e82da1263fd85bba4b38eb32a4..2afd9260a48d33d6f2abd7a0b0714d34b91dacfa 100644 (file)
--- a/litedram/generated/genesys2/litedram_core.v
+++ b/litedram/generated/genesys2/litedram_core.v
@@ -1,5 +1,5 @@
 //--------------------------------------------------------------------------------
-// Auto-generated by Migen (4fea1bd) & LiteX (83d24d08) on 2020-07-08 17:33:24
+// Auto-generated by Migen (--------) & LiteX (2ec4604c) on 2020-08-06 07:16:18
 //--------------------------------------------------------------------------------
 module litedram_core(
        input wire clk,
@@ -2120,14 +2120,12 @@ end
 reg dummy_d_1;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_adr <= 14'd0;
+       soc_litedramcore_wishbone_ack <= 1'd0;
        case (vns_state)
                1'd1: begin
+                       soc_litedramcore_wishbone_ack <= 1'd1;
                end
                default: begin
-                       if ((soc_litedramcore_wishbone_cyc & soc_litedramcore_wishbone_stb)) begin
-                               soc_litedramcore_adr <= soc_litedramcore_wishbone_adr;
-                       end
                end
        endcase
 // synthesis translate_off
@@ -2139,13 +2137,13 @@ end
 reg dummy_d_2;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_we <= 1'd0;
+       soc_litedramcore_adr <= 14'd0;
        case (vns_state)
                1'd1: begin
                end
                default: begin
                        if ((soc_litedramcore_wishbone_cyc & soc_litedramcore_wishbone_stb)) begin
-                               soc_litedramcore_we <= (soc_litedramcore_wishbone_we & (soc_litedramcore_wishbone_sel != 1'd0));
+                               soc_litedramcore_adr <= soc_litedramcore_wishbone_adr;
                        end
                end
        endcase
@@ -2158,12 +2156,14 @@ end
 reg dummy_d_3;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_wishbone_ack <= 1'd0;
+       soc_litedramcore_we <= 1'd0;
        case (vns_state)
                1'd1: begin
-                       soc_litedramcore_wishbone_ack <= 1'd1;
                end
                default: begin
+                       if ((soc_litedramcore_wishbone_cyc & soc_litedramcore_wishbone_stb)) begin
+                               soc_litedramcore_we <= (soc_litedramcore_wishbone_we & (soc_litedramcore_wishbone_sel != 1'd0));
+                       end
                end
        endcase
 // synthesis translate_off
@@ -2506,7 +2506,7 @@ assign soc_k7ddrphy_bitslip29_i = soc_k7ddrphy_dq_i_data29;
 assign soc_k7ddrphy_bitslip30_i = soc_k7ddrphy_dq_i_data30;
 assign soc_k7ddrphy_bitslip31_i = soc_k7ddrphy_dq_i_data31;
 assign soc_k7ddrphy_rddata_en = {soc_k7ddrphy_rddata_en_last, soc_k7ddrphy_dfi_p2_rddata_en};
-assign soc_k7ddrphy_wrdata_en = {soc_k7ddrphy_wrdata_en_last, soc_k7ddrphy_dfi_p3_wrdata_en};
+assign soc_k7ddrphy_wrdata_en = {soc_k7ddrphy_wrdata_en_last, soc_k7ddrphy_dfi_p2_wrdata_en};
 assign soc_k7ddrphy_dq_oe = soc_k7ddrphy_wrdata_en[2];
 
 // synthesis translate_off
@@ -4601,11 +4601,11 @@ assign soc_litedramcore_dfi_p3_rddata_valid = soc_litedramcore_slave_p3_rddata_v
 reg dummy_d_42;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_master_p1_ras_n <= 1'd1;
+       soc_litedramcore_master_p0_address <= 15'd0;
        if (soc_litedramcore_sel) begin
-               soc_litedramcore_master_p1_ras_n <= soc_litedramcore_slave_p1_ras_n;
+               soc_litedramcore_master_p0_address <= soc_litedramcore_slave_p0_address;
        end else begin
-               soc_litedramcore_master_p1_ras_n <= soc_litedramcore_inti_p1_ras_n;
+               soc_litedramcore_master_p0_address <= soc_litedramcore_inti_p0_address;
        end
 // synthesis translate_off
        dummy_d_42 = dummy_s;
@@ -4616,10 +4616,11 @@ end
 reg dummy_d_43;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_slave_p1_rddata <= 64'd0;
+       soc_litedramcore_master_p0_bank <= 3'd0;
        if (soc_litedramcore_sel) begin
-               soc_litedramcore_slave_p1_rddata <= soc_litedramcore_master_p1_rddata;
+               soc_litedramcore_master_p0_bank <= soc_litedramcore_slave_p0_bank;
        end else begin
+               soc_litedramcore_master_p0_bank <= soc_litedramcore_inti_p0_bank;
        end
 // synthesis translate_off
        dummy_d_43 = dummy_s;
@@ -4630,11 +4631,11 @@ end
 reg dummy_d_44;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_master_p1_we_n <= 1'd1;
+       soc_litedramcore_master_p0_cas_n <= 1'd1;
        if (soc_litedramcore_sel) begin
-               soc_litedramcore_master_p1_we_n <= soc_litedramcore_slave_p1_we_n;
+               soc_litedramcore_master_p0_cas_n <= soc_litedramcore_slave_p0_cas_n;
        end else begin
-               soc_litedramcore_master_p1_we_n <= soc_litedramcore_inti_p1_we_n;
+               soc_litedramcore_master_p0_cas_n <= soc_litedramcore_inti_p0_cas_n;
        end
 // synthesis translate_off
        dummy_d_44 = dummy_s;
@@ -4645,10 +4646,11 @@ end
 reg dummy_d_45;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_slave_p1_rddata_valid <= 1'd0;
+       soc_litedramcore_master_p0_cs_n <= 1'd1;
        if (soc_litedramcore_sel) begin
-               soc_litedramcore_slave_p1_rddata_valid <= soc_litedramcore_master_p1_rddata_valid;
+               soc_litedramcore_master_p0_cs_n <= soc_litedramcore_slave_p0_cs_n;
        end else begin
+               soc_litedramcore_master_p0_cs_n <= soc_litedramcore_inti_p0_cs_n;
        end
 // synthesis translate_off
        dummy_d_45 = dummy_s;
@@ -4659,11 +4661,11 @@ end
 reg dummy_d_46;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_master_p1_cke <= 1'd0;
+       soc_litedramcore_master_p0_ras_n <= 1'd1;
        if (soc_litedramcore_sel) begin
-               soc_litedramcore_master_p1_cke <= soc_litedramcore_slave_p1_cke;
+               soc_litedramcore_master_p0_ras_n <= soc_litedramcore_slave_p0_ras_n;
        end else begin
-               soc_litedramcore_master_p1_cke <= soc_litedramcore_inti_p1_cke;
+               soc_litedramcore_master_p0_ras_n <= soc_litedramcore_inti_p0_ras_n;
        end
 // synthesis translate_off
        dummy_d_46 = dummy_s;
@@ -4674,11 +4676,10 @@ end
 reg dummy_d_47;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_master_p1_odt <= 1'd0;
+       soc_litedramcore_slave_p0_rddata <= 64'd0;
        if (soc_litedramcore_sel) begin
-               soc_litedramcore_master_p1_odt <= soc_litedramcore_slave_p1_odt;
+               soc_litedramcore_slave_p0_rddata <= soc_litedramcore_master_p0_rddata;
        end else begin
-               soc_litedramcore_master_p1_odt <= soc_litedramcore_inti_p1_odt;
        end
 // synthesis translate_off
        dummy_d_47 = dummy_s;
@@ -4689,11 +4690,11 @@ end
 reg dummy_d_48;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_master_p1_reset_n <= 1'd0;
+       soc_litedramcore_master_p0_we_n <= 1'd1;
        if (soc_litedramcore_sel) begin
-               soc_litedramcore_master_p1_reset_n <= soc_litedramcore_slave_p1_reset_n;
+               soc_litedramcore_master_p0_we_n <= soc_litedramcore_slave_p0_we_n;
        end else begin
-               soc_litedramcore_master_p1_reset_n <= soc_litedramcore_inti_p1_reset_n;
+               soc_litedramcore_master_p0_we_n <= soc_litedramcore_inti_p0_we_n;
        end
 // synthesis translate_off
        dummy_d_48 = dummy_s;
@@ -4704,11 +4705,10 @@ end
 reg dummy_d_49;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_master_p1_act_n <= 1'd1;
+       soc_litedramcore_slave_p0_rddata_valid <= 1'd0;
        if (soc_litedramcore_sel) begin
-               soc_litedramcore_master_p1_act_n <= soc_litedramcore_slave_p1_act_n;
+               soc_litedramcore_slave_p0_rddata_valid <= soc_litedramcore_master_p0_rddata_valid;
        end else begin
-               soc_litedramcore_master_p1_act_n <= soc_litedramcore_inti_p1_act_n;
        end
 // synthesis translate_off
        dummy_d_49 = dummy_s;
@@ -4719,11 +4719,11 @@ end
 reg dummy_d_50;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_master_p1_wrdata <= 64'd0;
+       soc_litedramcore_master_p0_cke <= 1'd0;
        if (soc_litedramcore_sel) begin
-               soc_litedramcore_master_p1_wrdata <= soc_litedramcore_slave_p1_wrdata;
+               soc_litedramcore_master_p0_cke <= soc_litedramcore_slave_p0_cke;
        end else begin
-               soc_litedramcore_master_p1_wrdata <= soc_litedramcore_inti_p1_wrdata;
+               soc_litedramcore_master_p0_cke <= soc_litedramcore_inti_p0_cke;
        end
 // synthesis translate_off
        dummy_d_50 = dummy_s;
@@ -4734,10 +4734,11 @@ end
 reg dummy_d_51;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_inti_p2_rddata <= 64'd0;
+       soc_litedramcore_master_p0_odt <= 1'd0;
        if (soc_litedramcore_sel) begin
+               soc_litedramcore_master_p0_odt <= soc_litedramcore_slave_p0_odt;
        end else begin
-               soc_litedramcore_inti_p2_rddata <= soc_litedramcore_master_p2_rddata;
+               soc_litedramcore_master_p0_odt <= soc_litedramcore_inti_p0_odt;
        end
 // synthesis translate_off
        dummy_d_51 = dummy_s;
@@ -4748,11 +4749,11 @@ end
 reg dummy_d_52;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_master_p1_wrdata_en <= 1'd0;
+       soc_litedramcore_master_p0_reset_n <= 1'd0;
        if (soc_litedramcore_sel) begin
-               soc_litedramcore_master_p1_wrdata_en <= soc_litedramcore_slave_p1_wrdata_en;
+               soc_litedramcore_master_p0_reset_n <= soc_litedramcore_slave_p0_reset_n;
        end else begin
-               soc_litedramcore_master_p1_wrdata_en <= soc_litedramcore_inti_p1_wrdata_en;
+               soc_litedramcore_master_p0_reset_n <= soc_litedramcore_inti_p0_reset_n;
        end
 // synthesis translate_off
        dummy_d_52 = dummy_s;
@@ -4763,10 +4764,11 @@ end
 reg dummy_d_53;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_inti_p2_rddata_valid <= 1'd0;
+       soc_litedramcore_master_p0_act_n <= 1'd1;
        if (soc_litedramcore_sel) begin
+               soc_litedramcore_master_p0_act_n <= soc_litedramcore_slave_p0_act_n;
        end else begin
-               soc_litedramcore_inti_p2_rddata_valid <= soc_litedramcore_master_p2_rddata_valid;
+               soc_litedramcore_master_p0_act_n <= soc_litedramcore_inti_p0_act_n;
        end
 // synthesis translate_off
        dummy_d_53 = dummy_s;
@@ -4777,11 +4779,11 @@ end
 reg dummy_d_54;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_master_p1_wrdata_mask <= 8'd0;
+       soc_litedramcore_master_p0_wrdata <= 64'd0;
        if (soc_litedramcore_sel) begin
-               soc_litedramcore_master_p1_wrdata_mask <= soc_litedramcore_slave_p1_wrdata_mask;
+               soc_litedramcore_master_p0_wrdata <= soc_litedramcore_slave_p0_wrdata;
        end else begin
-               soc_litedramcore_master_p1_wrdata_mask <= soc_litedramcore_inti_p1_wrdata_mask;
+               soc_litedramcore_master_p0_wrdata <= soc_litedramcore_inti_p0_wrdata;
        end
 // synthesis translate_off
        dummy_d_54 = dummy_s;
@@ -4792,11 +4794,10 @@ end
 reg dummy_d_55;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_master_p1_rddata_en <= 1'd0;
+       soc_litedramcore_inti_p1_rddata <= 64'd0;
        if (soc_litedramcore_sel) begin
-               soc_litedramcore_master_p1_rddata_en <= soc_litedramcore_slave_p1_rddata_en;
        end else begin
-               soc_litedramcore_master_p1_rddata_en <= soc_litedramcore_inti_p1_rddata_en;
+               soc_litedramcore_inti_p1_rddata <= soc_litedramcore_master_p1_rddata;
        end
 // synthesis translate_off
        dummy_d_55 = dummy_s;
@@ -4807,11 +4808,11 @@ end
 reg dummy_d_56;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_master_p2_address <= 15'd0;
+       soc_litedramcore_master_p0_wrdata_en <= 1'd0;
        if (soc_litedramcore_sel) begin
-               soc_litedramcore_master_p2_address <= soc_litedramcore_slave_p2_address;
+               soc_litedramcore_master_p0_wrdata_en <= soc_litedramcore_slave_p0_wrdata_en;
        end else begin
-               soc_litedramcore_master_p2_address <= soc_litedramcore_inti_p2_address;
+               soc_litedramcore_master_p0_wrdata_en <= soc_litedramcore_inti_p0_wrdata_en;
        end
 // synthesis translate_off
        dummy_d_56 = dummy_s;
@@ -4822,11 +4823,10 @@ end
 reg dummy_d_57;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_master_p2_bank <= 3'd0;
+       soc_litedramcore_inti_p1_rddata_valid <= 1'd0;
        if (soc_litedramcore_sel) begin
-               soc_litedramcore_master_p2_bank <= soc_litedramcore_slave_p2_bank;
        end else begin
-               soc_litedramcore_master_p2_bank <= soc_litedramcore_inti_p2_bank;
+               soc_litedramcore_inti_p1_rddata_valid <= soc_litedramcore_master_p1_rddata_valid;
        end
 // synthesis translate_off
        dummy_d_57 = dummy_s;
@@ -4837,11 +4837,11 @@ end
 reg dummy_d_58;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_master_p2_cas_n <= 1'd1;
+       soc_litedramcore_master_p0_wrdata_mask <= 8'd0;
        if (soc_litedramcore_sel) begin
-               soc_litedramcore_master_p2_cas_n <= soc_litedramcore_slave_p2_cas_n;
+               soc_litedramcore_master_p0_wrdata_mask <= soc_litedramcore_slave_p0_wrdata_mask;
        end else begin
-               soc_litedramcore_master_p2_cas_n <= soc_litedramcore_inti_p2_cas_n;
+               soc_litedramcore_master_p0_wrdata_mask <= soc_litedramcore_inti_p0_wrdata_mask;
        end
 // synthesis translate_off
        dummy_d_58 = dummy_s;
@@ -4852,11 +4852,11 @@ end
 reg dummy_d_59;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_master_p2_cs_n <= 1'd1;
+       soc_litedramcore_master_p0_rddata_en <= 1'd0;
        if (soc_litedramcore_sel) begin
-               soc_litedramcore_master_p2_cs_n <= soc_litedramcore_slave_p2_cs_n;
+               soc_litedramcore_master_p0_rddata_en <= soc_litedramcore_slave_p0_rddata_en;
        end else begin
-               soc_litedramcore_master_p2_cs_n <= soc_litedramcore_inti_p2_cs_n;
+               soc_litedramcore_master_p0_rddata_en <= soc_litedramcore_inti_p0_rddata_en;
        end
 // synthesis translate_off
        dummy_d_59 = dummy_s;
@@ -4867,11 +4867,11 @@ end
 reg dummy_d_60;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_master_p2_ras_n <= 1'd1;
+       soc_litedramcore_master_p1_address <= 15'd0;
        if (soc_litedramcore_sel) begin
-               soc_litedramcore_master_p2_ras_n <= soc_litedramcore_slave_p2_ras_n;
+               soc_litedramcore_master_p1_address <= soc_litedramcore_slave_p1_address;
        end else begin
-               soc_litedramcore_master_p2_ras_n <= soc_litedramcore_inti_p2_ras_n;
+               soc_litedramcore_master_p1_address <= soc_litedramcore_inti_p1_address;
        end
 // synthesis translate_off
        dummy_d_60 = dummy_s;
@@ -4882,10 +4882,10 @@ end
 reg dummy_d_61;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_slave_p2_rddata <= 64'd0;
+       soc_litedramcore_inti_p0_rddata <= 64'd0;
        if (soc_litedramcore_sel) begin
-               soc_litedramcore_slave_p2_rddata <= soc_litedramcore_master_p2_rddata;
        end else begin
+               soc_litedramcore_inti_p0_rddata <= soc_litedramcore_master_p0_rddata;
        end
 // synthesis translate_off
        dummy_d_61 = dummy_s;
@@ -4896,11 +4896,11 @@ end
 reg dummy_d_62;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_master_p2_we_n <= 1'd1;
+       soc_litedramcore_master_p1_bank <= 3'd0;
        if (soc_litedramcore_sel) begin
-               soc_litedramcore_master_p2_we_n <= soc_litedramcore_slave_p2_we_n;
+               soc_litedramcore_master_p1_bank <= soc_litedramcore_slave_p1_bank;
        end else begin
-               soc_litedramcore_master_p2_we_n <= soc_litedramcore_inti_p2_we_n;
+               soc_litedramcore_master_p1_bank <= soc_litedramcore_inti_p1_bank;
        end
 // synthesis translate_off
        dummy_d_62 = dummy_s;
@@ -4911,10 +4911,11 @@ end
 reg dummy_d_63;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_slave_p2_rddata_valid <= 1'd0;
+       soc_litedramcore_master_p1_cas_n <= 1'd1;
        if (soc_litedramcore_sel) begin
-               soc_litedramcore_slave_p2_rddata_valid <= soc_litedramcore_master_p2_rddata_valid;
+               soc_litedramcore_master_p1_cas_n <= soc_litedramcore_slave_p1_cas_n;
        end else begin
+               soc_litedramcore_master_p1_cas_n <= soc_litedramcore_inti_p1_cas_n;
        end
 // synthesis translate_off
        dummy_d_63 = dummy_s;
@@ -4925,11 +4926,11 @@ end
 reg dummy_d_64;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_master_p2_cke <= 1'd0;
+       soc_litedramcore_master_p1_cs_n <= 1'd1;
        if (soc_litedramcore_sel) begin
-               soc_litedramcore_master_p2_cke <= soc_litedramcore_slave_p2_cke;
+               soc_litedramcore_master_p1_cs_n <= soc_litedramcore_slave_p1_cs_n;
        end else begin
-               soc_litedramcore_master_p2_cke <= soc_litedramcore_inti_p2_cke;
+               soc_litedramcore_master_p1_cs_n <= soc_litedramcore_inti_p1_cs_n;
        end
 // synthesis translate_off
        dummy_d_64 = dummy_s;
@@ -4940,11 +4941,11 @@ end
 reg dummy_d_65;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_master_p2_odt <= 1'd0;
+       soc_litedramcore_master_p1_ras_n <= 1'd1;
        if (soc_litedramcore_sel) begin
-               soc_litedramcore_master_p2_odt <= soc_litedramcore_slave_p2_odt;
+               soc_litedramcore_master_p1_ras_n <= soc_litedramcore_slave_p1_ras_n;
        end else begin
-               soc_litedramcore_master_p2_odt <= soc_litedramcore_inti_p2_odt;
+               soc_litedramcore_master_p1_ras_n <= soc_litedramcore_inti_p1_ras_n;
        end
 // synthesis translate_off
        dummy_d_65 = dummy_s;
@@ -4955,11 +4956,10 @@ end
 reg dummy_d_66;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_master_p2_reset_n <= 1'd0;
+       soc_litedramcore_slave_p1_rddata <= 64'd0;
        if (soc_litedramcore_sel) begin
-               soc_litedramcore_master_p2_reset_n <= soc_litedramcore_slave_p2_reset_n;
+               soc_litedramcore_slave_p1_rddata <= soc_litedramcore_master_p1_rddata;
        end else begin
-               soc_litedramcore_master_p2_reset_n <= soc_litedramcore_inti_p2_reset_n;
        end
 // synthesis translate_off
        dummy_d_66 = dummy_s;
@@ -4970,11 +4970,11 @@ end
 reg dummy_d_67;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_master_p2_act_n <= 1'd1;
+       soc_litedramcore_master_p1_we_n <= 1'd1;
        if (soc_litedramcore_sel) begin
-               soc_litedramcore_master_p2_act_n <= soc_litedramcore_slave_p2_act_n;
+               soc_litedramcore_master_p1_we_n <= soc_litedramcore_slave_p1_we_n;
        end else begin
-               soc_litedramcore_master_p2_act_n <= soc_litedramcore_inti_p2_act_n;
+               soc_litedramcore_master_p1_we_n <= soc_litedramcore_inti_p1_we_n;
        end
 // synthesis translate_off
        dummy_d_67 = dummy_s;
@@ -4985,11 +4985,10 @@ end
 reg dummy_d_68;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_master_p2_wrdata <= 64'd0;
+       soc_litedramcore_slave_p1_rddata_valid <= 1'd0;
        if (soc_litedramcore_sel) begin
-               soc_litedramcore_master_p2_wrdata <= soc_litedramcore_slave_p2_wrdata;
+               soc_litedramcore_slave_p1_rddata_valid <= soc_litedramcore_master_p1_rddata_valid;
        end else begin
-               soc_litedramcore_master_p2_wrdata <= soc_litedramcore_inti_p2_wrdata;
        end
 // synthesis translate_off
        dummy_d_68 = dummy_s;
@@ -5000,10 +4999,11 @@ end
 reg dummy_d_69;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_inti_p3_rddata <= 64'd0;
+       soc_litedramcore_master_p1_cke <= 1'd0;
        if (soc_litedramcore_sel) begin
+               soc_litedramcore_master_p1_cke <= soc_litedramcore_slave_p1_cke;
        end else begin
-               soc_litedramcore_inti_p3_rddata <= soc_litedramcore_master_p3_rddata;
+               soc_litedramcore_master_p1_cke <= soc_litedramcore_inti_p1_cke;
        end
 // synthesis translate_off
        dummy_d_69 = dummy_s;
@@ -5014,11 +5014,10 @@ end
 reg dummy_d_70;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_master_p2_wrdata_en <= 1'd0;
+       soc_litedramcore_inti_p0_rddata_valid <= 1'd0;
        if (soc_litedramcore_sel) begin
-               soc_litedramcore_master_p2_wrdata_en <= soc_litedramcore_slave_p2_wrdata_en;
        end else begin
-               soc_litedramcore_master_p2_wrdata_en <= soc_litedramcore_inti_p2_wrdata_en;
+               soc_litedramcore_inti_p0_rddata_valid <= soc_litedramcore_master_p0_rddata_valid;
        end
 // synthesis translate_off
        dummy_d_70 = dummy_s;
@@ -5029,10 +5028,11 @@ end
 reg dummy_d_71;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_inti_p3_rddata_valid <= 1'd0;
+       soc_litedramcore_master_p1_odt <= 1'd0;
        if (soc_litedramcore_sel) begin
+               soc_litedramcore_master_p1_odt <= soc_litedramcore_slave_p1_odt;
        end else begin
-               soc_litedramcore_inti_p3_rddata_valid <= soc_litedramcore_master_p3_rddata_valid;
+               soc_litedramcore_master_p1_odt <= soc_litedramcore_inti_p1_odt;
        end
 // synthesis translate_off
        dummy_d_71 = dummy_s;
@@ -5043,11 +5043,11 @@ end
 reg dummy_d_72;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_master_p2_wrdata_mask <= 8'd0;
+       soc_litedramcore_master_p1_reset_n <= 1'd0;
        if (soc_litedramcore_sel) begin
-               soc_litedramcore_master_p2_wrdata_mask <= soc_litedramcore_slave_p2_wrdata_mask;
+               soc_litedramcore_master_p1_reset_n <= soc_litedramcore_slave_p1_reset_n;
        end else begin
-               soc_litedramcore_master_p2_wrdata_mask <= soc_litedramcore_inti_p2_wrdata_mask;
+               soc_litedramcore_master_p1_reset_n <= soc_litedramcore_inti_p1_reset_n;
        end
 // synthesis translate_off
        dummy_d_72 = dummy_s;
@@ -5058,11 +5058,11 @@ end
 reg dummy_d_73;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_master_p2_rddata_en <= 1'd0;
+       soc_litedramcore_master_p1_act_n <= 1'd1;
        if (soc_litedramcore_sel) begin
-               soc_litedramcore_master_p2_rddata_en <= soc_litedramcore_slave_p2_rddata_en;
+               soc_litedramcore_master_p1_act_n <= soc_litedramcore_slave_p1_act_n;
        end else begin
-               soc_litedramcore_master_p2_rddata_en <= soc_litedramcore_inti_p2_rddata_en;
+               soc_litedramcore_master_p1_act_n <= soc_litedramcore_inti_p1_act_n;
        end
 // synthesis translate_off
        dummy_d_73 = dummy_s;
@@ -5073,11 +5073,11 @@ end
 reg dummy_d_74;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_master_p3_address <= 15'd0;
+       soc_litedramcore_master_p1_wrdata <= 64'd0;
        if (soc_litedramcore_sel) begin
-               soc_litedramcore_master_p3_address <= soc_litedramcore_slave_p3_address;
+               soc_litedramcore_master_p1_wrdata <= soc_litedramcore_slave_p1_wrdata;
        end else begin
-               soc_litedramcore_master_p3_address <= soc_litedramcore_inti_p3_address;
+               soc_litedramcore_master_p1_wrdata <= soc_litedramcore_inti_p1_wrdata;
        end
 // synthesis translate_off
        dummy_d_74 = dummy_s;
@@ -5088,11 +5088,10 @@ end
 reg dummy_d_75;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_master_p3_bank <= 3'd0;
+       soc_litedramcore_inti_p2_rddata <= 64'd0;
        if (soc_litedramcore_sel) begin
-               soc_litedramcore_master_p3_bank <= soc_litedramcore_slave_p3_bank;
        end else begin
-               soc_litedramcore_master_p3_bank <= soc_litedramcore_inti_p3_bank;
+               soc_litedramcore_inti_p2_rddata <= soc_litedramcore_master_p2_rddata;
        end
 // synthesis translate_off
        dummy_d_75 = dummy_s;
@@ -5103,11 +5102,11 @@ end
 reg dummy_d_76;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_master_p3_cas_n <= 1'd1;
+       soc_litedramcore_master_p1_wrdata_en <= 1'd0;
        if (soc_litedramcore_sel) begin
-               soc_litedramcore_master_p3_cas_n <= soc_litedramcore_slave_p3_cas_n;
+               soc_litedramcore_master_p1_wrdata_en <= soc_litedramcore_slave_p1_wrdata_en;
        end else begin
-               soc_litedramcore_master_p3_cas_n <= soc_litedramcore_inti_p3_cas_n;
+               soc_litedramcore_master_p1_wrdata_en <= soc_litedramcore_inti_p1_wrdata_en;
        end
 // synthesis translate_off
        dummy_d_76 = dummy_s;
@@ -5118,11 +5117,10 @@ end
 reg dummy_d_77;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_master_p3_cs_n <= 1'd1;
+       soc_litedramcore_inti_p2_rddata_valid <= 1'd0;
        if (soc_litedramcore_sel) begin
-               soc_litedramcore_master_p3_cs_n <= soc_litedramcore_slave_p3_cs_n;
        end else begin
-               soc_litedramcore_master_p3_cs_n <= soc_litedramcore_inti_p3_cs_n;
+               soc_litedramcore_inti_p2_rddata_valid <= soc_litedramcore_master_p2_rddata_valid;
        end
 // synthesis translate_off
        dummy_d_77 = dummy_s;
@@ -5133,11 +5131,11 @@ end
 reg dummy_d_78;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_master_p3_ras_n <= 1'd1;
+       soc_litedramcore_master_p1_wrdata_mask <= 8'd0;
        if (soc_litedramcore_sel) begin
-               soc_litedramcore_master_p3_ras_n <= soc_litedramcore_slave_p3_ras_n;
+               soc_litedramcore_master_p1_wrdata_mask <= soc_litedramcore_slave_p1_wrdata_mask;
        end else begin
-               soc_litedramcore_master_p3_ras_n <= soc_litedramcore_inti_p3_ras_n;
+               soc_litedramcore_master_p1_wrdata_mask <= soc_litedramcore_inti_p1_wrdata_mask;
        end
 // synthesis translate_off
        dummy_d_78 = dummy_s;
@@ -5148,10 +5146,11 @@ end
 reg dummy_d_79;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_slave_p3_rddata <= 64'd0;
+       soc_litedramcore_master_p1_rddata_en <= 1'd0;
        if (soc_litedramcore_sel) begin
-               soc_litedramcore_slave_p3_rddata <= soc_litedramcore_master_p3_rddata;
+               soc_litedramcore_master_p1_rddata_en <= soc_litedramcore_slave_p1_rddata_en;
        end else begin
+               soc_litedramcore_master_p1_rddata_en <= soc_litedramcore_inti_p1_rddata_en;
        end
 // synthesis translate_off
        dummy_d_79 = dummy_s;
@@ -5162,11 +5161,11 @@ end
 reg dummy_d_80;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_master_p3_we_n <= 1'd1;
+       soc_litedramcore_master_p2_address <= 15'd0;
        if (soc_litedramcore_sel) begin
-               soc_litedramcore_master_p3_we_n <= soc_litedramcore_slave_p3_we_n;
+               soc_litedramcore_master_p2_address <= soc_litedramcore_slave_p2_address;
        end else begin
-               soc_litedramcore_master_p3_we_n <= soc_litedramcore_inti_p3_we_n;
+               soc_litedramcore_master_p2_address <= soc_litedramcore_inti_p2_address;
        end
 // synthesis translate_off
        dummy_d_80 = dummy_s;
@@ -5177,10 +5176,11 @@ end
 reg dummy_d_81;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_slave_p3_rddata_valid <= 1'd0;
+       soc_litedramcore_master_p2_bank <= 3'd0;
        if (soc_litedramcore_sel) begin
-               soc_litedramcore_slave_p3_rddata_valid <= soc_litedramcore_master_p3_rddata_valid;
+               soc_litedramcore_master_p2_bank <= soc_litedramcore_slave_p2_bank;
        end else begin
+               soc_litedramcore_master_p2_bank <= soc_litedramcore_inti_p2_bank;
        end
 // synthesis translate_off
        dummy_d_81 = dummy_s;
@@ -5191,11 +5191,11 @@ end
 reg dummy_d_82;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_master_p3_cke <= 1'd0;
+       soc_litedramcore_master_p2_cas_n <= 1'd1;
        if (soc_litedramcore_sel) begin
-               soc_litedramcore_master_p3_cke <= soc_litedramcore_slave_p3_cke;
+               soc_litedramcore_master_p2_cas_n <= soc_litedramcore_slave_p2_cas_n;
        end else begin
-               soc_litedramcore_master_p3_cke <= soc_litedramcore_inti_p3_cke;
+               soc_litedramcore_master_p2_cas_n <= soc_litedramcore_inti_p2_cas_n;
        end
 // synthesis translate_off
        dummy_d_82 = dummy_s;
@@ -5206,11 +5206,11 @@ end
 reg dummy_d_83;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_master_p3_odt <= 1'd0;
+       soc_litedramcore_master_p2_cs_n <= 1'd1;
        if (soc_litedramcore_sel) begin
-               soc_litedramcore_master_p3_odt <= soc_litedramcore_slave_p3_odt;
+               soc_litedramcore_master_p2_cs_n <= soc_litedramcore_slave_p2_cs_n;
        end else begin
-               soc_litedramcore_master_p3_odt <= soc_litedramcore_inti_p3_odt;
+               soc_litedramcore_master_p2_cs_n <= soc_litedramcore_inti_p2_cs_n;
        end
 // synthesis translate_off
        dummy_d_83 = dummy_s;
@@ -5221,11 +5221,11 @@ end
 reg dummy_d_84;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_master_p3_reset_n <= 1'd0;
+       soc_litedramcore_master_p2_ras_n <= 1'd1;
        if (soc_litedramcore_sel) begin
-               soc_litedramcore_master_p3_reset_n <= soc_litedramcore_slave_p3_reset_n;
+               soc_litedramcore_master_p2_ras_n <= soc_litedramcore_slave_p2_ras_n;
        end else begin
-               soc_litedramcore_master_p3_reset_n <= soc_litedramcore_inti_p3_reset_n;
+               soc_litedramcore_master_p2_ras_n <= soc_litedramcore_inti_p2_ras_n;
        end
 // synthesis translate_off
        dummy_d_84 = dummy_s;
@@ -5236,11 +5236,10 @@ end
 reg dummy_d_85;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_master_p3_act_n <= 1'd1;
+       soc_litedramcore_slave_p2_rddata <= 64'd0;
        if (soc_litedramcore_sel) begin
-               soc_litedramcore_master_p3_act_n <= soc_litedramcore_slave_p3_act_n;
+               soc_litedramcore_slave_p2_rddata <= soc_litedramcore_master_p2_rddata;
        end else begin
-               soc_litedramcore_master_p3_act_n <= soc_litedramcore_inti_p3_act_n;
        end
 // synthesis translate_off
        dummy_d_85 = dummy_s;
@@ -5251,11 +5250,11 @@ end
 reg dummy_d_86;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_master_p3_wrdata <= 64'd0;
+       soc_litedramcore_master_p2_we_n <= 1'd1;
        if (soc_litedramcore_sel) begin
-               soc_litedramcore_master_p3_wrdata <= soc_litedramcore_slave_p3_wrdata;
+               soc_litedramcore_master_p2_we_n <= soc_litedramcore_slave_p2_we_n;
        end else begin
-               soc_litedramcore_master_p3_wrdata <= soc_litedramcore_inti_p3_wrdata;
+               soc_litedramcore_master_p2_we_n <= soc_litedramcore_inti_p2_we_n;
        end
 // synthesis translate_off
        dummy_d_86 = dummy_s;
@@ -5266,10 +5265,10 @@ end
 reg dummy_d_87;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_inti_p0_rddata <= 64'd0;
+       soc_litedramcore_slave_p2_rddata_valid <= 1'd0;
        if (soc_litedramcore_sel) begin
+               soc_litedramcore_slave_p2_rddata_valid <= soc_litedramcore_master_p2_rddata_valid;
        end else begin
-               soc_litedramcore_inti_p0_rddata <= soc_litedramcore_master_p0_rddata;
        end
 // synthesis translate_off
        dummy_d_87 = dummy_s;
@@ -5280,11 +5279,11 @@ end
 reg dummy_d_88;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_master_p3_wrdata_en <= 1'd0;
+       soc_litedramcore_master_p2_cke <= 1'd0;
        if (soc_litedramcore_sel) begin
-               soc_litedramcore_master_p3_wrdata_en <= soc_litedramcore_slave_p3_wrdata_en;
+               soc_litedramcore_master_p2_cke <= soc_litedramcore_slave_p2_cke;
        end else begin
-               soc_litedramcore_master_p3_wrdata_en <= soc_litedramcore_inti_p3_wrdata_en;
+               soc_litedramcore_master_p2_cke <= soc_litedramcore_inti_p2_cke;
        end
 // synthesis translate_off
        dummy_d_88 = dummy_s;
@@ -5295,10 +5294,11 @@ end
 reg dummy_d_89;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_inti_p0_rddata_valid <= 1'd0;
+       soc_litedramcore_master_p2_odt <= 1'd0;
        if (soc_litedramcore_sel) begin
+               soc_litedramcore_master_p2_odt <= soc_litedramcore_slave_p2_odt;
        end else begin
-               soc_litedramcore_inti_p0_rddata_valid <= soc_litedramcore_master_p0_rddata_valid;
+               soc_litedramcore_master_p2_odt <= soc_litedramcore_inti_p2_odt;
        end
 // synthesis translate_off
        dummy_d_89 = dummy_s;
@@ -5309,11 +5309,11 @@ end
 reg dummy_d_90;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_master_p3_wrdata_mask <= 8'd0;
+       soc_litedramcore_master_p2_reset_n <= 1'd0;
        if (soc_litedramcore_sel) begin
-               soc_litedramcore_master_p3_wrdata_mask <= soc_litedramcore_slave_p3_wrdata_mask;
+               soc_litedramcore_master_p2_reset_n <= soc_litedramcore_slave_p2_reset_n;
        end else begin
-               soc_litedramcore_master_p3_wrdata_mask <= soc_litedramcore_inti_p3_wrdata_mask;
+               soc_litedramcore_master_p2_reset_n <= soc_litedramcore_inti_p2_reset_n;
        end
 // synthesis translate_off
        dummy_d_90 = dummy_s;
@@ -5324,11 +5324,11 @@ end
 reg dummy_d_91;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_master_p3_rddata_en <= 1'd0;
+       soc_litedramcore_master_p2_act_n <= 1'd1;
        if (soc_litedramcore_sel) begin
-               soc_litedramcore_master_p3_rddata_en <= soc_litedramcore_slave_p3_rddata_en;
+               soc_litedramcore_master_p2_act_n <= soc_litedramcore_slave_p2_act_n;
        end else begin
-               soc_litedramcore_master_p3_rddata_en <= soc_litedramcore_inti_p3_rddata_en;
+               soc_litedramcore_master_p2_act_n <= soc_litedramcore_inti_p2_act_n;
        end
 // synthesis translate_off
        dummy_d_91 = dummy_s;
@@ -5339,11 +5339,11 @@ end
 reg dummy_d_92;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_master_p0_address <= 15'd0;
+       soc_litedramcore_master_p2_wrdata <= 64'd0;
        if (soc_litedramcore_sel) begin
-               soc_litedramcore_master_p0_address <= soc_litedramcore_slave_p0_address;
+               soc_litedramcore_master_p2_wrdata <= soc_litedramcore_slave_p2_wrdata;
        end else begin
-               soc_litedramcore_master_p0_address <= soc_litedramcore_inti_p0_address;
+               soc_litedramcore_master_p2_wrdata <= soc_litedramcore_inti_p2_wrdata;
        end
 // synthesis translate_off
        dummy_d_92 = dummy_s;
@@ -5354,11 +5354,10 @@ end
 reg dummy_d_93;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_master_p0_bank <= 3'd0;
+       soc_litedramcore_inti_p3_rddata <= 64'd0;
        if (soc_litedramcore_sel) begin
-               soc_litedramcore_master_p0_bank <= soc_litedramcore_slave_p0_bank;
        end else begin
-               soc_litedramcore_master_p0_bank <= soc_litedramcore_inti_p0_bank;
+               soc_litedramcore_inti_p3_rddata <= soc_litedramcore_master_p3_rddata;
        end
 // synthesis translate_off
        dummy_d_93 = dummy_s;
@@ -5369,11 +5368,11 @@ end
 reg dummy_d_94;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_master_p0_cas_n <= 1'd1;
+       soc_litedramcore_master_p2_wrdata_en <= 1'd0;
        if (soc_litedramcore_sel) begin
-               soc_litedramcore_master_p0_cas_n <= soc_litedramcore_slave_p0_cas_n;
+               soc_litedramcore_master_p2_wrdata_en <= soc_litedramcore_slave_p2_wrdata_en;
        end else begin
-               soc_litedramcore_master_p0_cas_n <= soc_litedramcore_inti_p0_cas_n;
+               soc_litedramcore_master_p2_wrdata_en <= soc_litedramcore_inti_p2_wrdata_en;
        end
 // synthesis translate_off
        dummy_d_94 = dummy_s;
@@ -5384,11 +5383,10 @@ end
 reg dummy_d_95;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_master_p0_cs_n <= 1'd1;
+       soc_litedramcore_inti_p3_rddata_valid <= 1'd0;
        if (soc_litedramcore_sel) begin
-               soc_litedramcore_master_p0_cs_n <= soc_litedramcore_slave_p0_cs_n;
        end else begin
-               soc_litedramcore_master_p0_cs_n <= soc_litedramcore_inti_p0_cs_n;
+               soc_litedramcore_inti_p3_rddata_valid <= soc_litedramcore_master_p3_rddata_valid;
        end
 // synthesis translate_off
        dummy_d_95 = dummy_s;
@@ -5399,11 +5397,11 @@ end
 reg dummy_d_96;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_master_p0_ras_n <= 1'd1;
+       soc_litedramcore_master_p2_wrdata_mask <= 8'd0;
        if (soc_litedramcore_sel) begin
-               soc_litedramcore_master_p0_ras_n <= soc_litedramcore_slave_p0_ras_n;
+               soc_litedramcore_master_p2_wrdata_mask <= soc_litedramcore_slave_p2_wrdata_mask;
        end else begin
-               soc_litedramcore_master_p0_ras_n <= soc_litedramcore_inti_p0_ras_n;
+               soc_litedramcore_master_p2_wrdata_mask <= soc_litedramcore_inti_p2_wrdata_mask;
        end
 // synthesis translate_off
        dummy_d_96 = dummy_s;
@@ -5414,10 +5412,11 @@ end
 reg dummy_d_97;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_slave_p0_rddata <= 64'd0;
+       soc_litedramcore_master_p2_rddata_en <= 1'd0;
        if (soc_litedramcore_sel) begin
-               soc_litedramcore_slave_p0_rddata <= soc_litedramcore_master_p0_rddata;
+               soc_litedramcore_master_p2_rddata_en <= soc_litedramcore_slave_p2_rddata_en;
        end else begin
+               soc_litedramcore_master_p2_rddata_en <= soc_litedramcore_inti_p2_rddata_en;
        end
 // synthesis translate_off
        dummy_d_97 = dummy_s;
@@ -5428,11 +5427,11 @@ end
 reg dummy_d_98;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_master_p0_we_n <= 1'd1;
+       soc_litedramcore_master_p3_address <= 15'd0;
        if (soc_litedramcore_sel) begin
-               soc_litedramcore_master_p0_we_n <= soc_litedramcore_slave_p0_we_n;
+               soc_litedramcore_master_p3_address <= soc_litedramcore_slave_p3_address;
        end else begin
-               soc_litedramcore_master_p0_we_n <= soc_litedramcore_inti_p0_we_n;
+               soc_litedramcore_master_p3_address <= soc_litedramcore_inti_p3_address;
        end
 // synthesis translate_off
        dummy_d_98 = dummy_s;
@@ -5443,10 +5442,11 @@ end
 reg dummy_d_99;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_slave_p0_rddata_valid <= 1'd0;
+       soc_litedramcore_master_p3_bank <= 3'd0;
        if (soc_litedramcore_sel) begin
-               soc_litedramcore_slave_p0_rddata_valid <= soc_litedramcore_master_p0_rddata_valid;
+               soc_litedramcore_master_p3_bank <= soc_litedramcore_slave_p3_bank;
        end else begin
+               soc_litedramcore_master_p3_bank <= soc_litedramcore_inti_p3_bank;
        end
 // synthesis translate_off
        dummy_d_99 = dummy_s;
@@ -5457,11 +5457,11 @@ end
 reg dummy_d_100;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_master_p0_cke <= 1'd0;
+       soc_litedramcore_master_p3_cas_n <= 1'd1;
        if (soc_litedramcore_sel) begin
-               soc_litedramcore_master_p0_cke <= soc_litedramcore_slave_p0_cke;
+               soc_litedramcore_master_p3_cas_n <= soc_litedramcore_slave_p3_cas_n;
        end else begin
-               soc_litedramcore_master_p0_cke <= soc_litedramcore_inti_p0_cke;
+               soc_litedramcore_master_p3_cas_n <= soc_litedramcore_inti_p3_cas_n;
        end
 // synthesis translate_off
        dummy_d_100 = dummy_s;
@@ -5472,11 +5472,11 @@ end
 reg dummy_d_101;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_master_p0_odt <= 1'd0;
+       soc_litedramcore_master_p3_cs_n <= 1'd1;
        if (soc_litedramcore_sel) begin
-               soc_litedramcore_master_p0_odt <= soc_litedramcore_slave_p0_odt;
+               soc_litedramcore_master_p3_cs_n <= soc_litedramcore_slave_p3_cs_n;
        end else begin
-               soc_litedramcore_master_p0_odt <= soc_litedramcore_inti_p0_odt;
+               soc_litedramcore_master_p3_cs_n <= soc_litedramcore_inti_p3_cs_n;
        end
 // synthesis translate_off
        dummy_d_101 = dummy_s;
@@ -5487,11 +5487,11 @@ end
 reg dummy_d_102;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_master_p0_reset_n <= 1'd0;
+       soc_litedramcore_master_p3_ras_n <= 1'd1;
        if (soc_litedramcore_sel) begin
-               soc_litedramcore_master_p0_reset_n <= soc_litedramcore_slave_p0_reset_n;
+               soc_litedramcore_master_p3_ras_n <= soc_litedramcore_slave_p3_ras_n;
        end else begin
-               soc_litedramcore_master_p0_reset_n <= soc_litedramcore_inti_p0_reset_n;
+               soc_litedramcore_master_p3_ras_n <= soc_litedramcore_inti_p3_ras_n;
        end
 // synthesis translate_off
        dummy_d_102 = dummy_s;
@@ -5502,11 +5502,10 @@ end
 reg dummy_d_103;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_master_p0_act_n <= 1'd1;
+       soc_litedramcore_slave_p3_rddata <= 64'd0;
        if (soc_litedramcore_sel) begin
-               soc_litedramcore_master_p0_act_n <= soc_litedramcore_slave_p0_act_n;
+               soc_litedramcore_slave_p3_rddata <= soc_litedramcore_master_p3_rddata;
        end else begin
-               soc_litedramcore_master_p0_act_n <= soc_litedramcore_inti_p0_act_n;
        end
 // synthesis translate_off
        dummy_d_103 = dummy_s;
@@ -5517,11 +5516,11 @@ end
 reg dummy_d_104;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_master_p0_wrdata <= 64'd0;
+       soc_litedramcore_master_p3_we_n <= 1'd1;
        if (soc_litedramcore_sel) begin
-               soc_litedramcore_master_p0_wrdata <= soc_litedramcore_slave_p0_wrdata;
+               soc_litedramcore_master_p3_we_n <= soc_litedramcore_slave_p3_we_n;
        end else begin
-               soc_litedramcore_master_p0_wrdata <= soc_litedramcore_inti_p0_wrdata;
+               soc_litedramcore_master_p3_we_n <= soc_litedramcore_inti_p3_we_n;
        end
 // synthesis translate_off
        dummy_d_104 = dummy_s;
@@ -5532,10 +5531,10 @@ end
 reg dummy_d_105;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_inti_p1_rddata <= 64'd0;
+       soc_litedramcore_slave_p3_rddata_valid <= 1'd0;
        if (soc_litedramcore_sel) begin
+               soc_litedramcore_slave_p3_rddata_valid <= soc_litedramcore_master_p3_rddata_valid;
        end else begin
-               soc_litedramcore_inti_p1_rddata <= soc_litedramcore_master_p1_rddata;
        end
 // synthesis translate_off
        dummy_d_105 = dummy_s;
@@ -5546,11 +5545,11 @@ end
 reg dummy_d_106;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_master_p0_wrdata_en <= 1'd0;
+       soc_litedramcore_master_p3_cke <= 1'd0;
        if (soc_litedramcore_sel) begin
-               soc_litedramcore_master_p0_wrdata_en <= soc_litedramcore_slave_p0_wrdata_en;
+               soc_litedramcore_master_p3_cke <= soc_litedramcore_slave_p3_cke;
        end else begin
-               soc_litedramcore_master_p0_wrdata_en <= soc_litedramcore_inti_p0_wrdata_en;
+               soc_litedramcore_master_p3_cke <= soc_litedramcore_inti_p3_cke;
        end
 // synthesis translate_off
        dummy_d_106 = dummy_s;
@@ -5561,10 +5560,11 @@ end
 reg dummy_d_107;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_inti_p1_rddata_valid <= 1'd0;
+       soc_litedramcore_master_p3_odt <= 1'd0;
        if (soc_litedramcore_sel) begin
+               soc_litedramcore_master_p3_odt <= soc_litedramcore_slave_p3_odt;
        end else begin
-               soc_litedramcore_inti_p1_rddata_valid <= soc_litedramcore_master_p1_rddata_valid;
+               soc_litedramcore_master_p3_odt <= soc_litedramcore_inti_p3_odt;
        end
 // synthesis translate_off
        dummy_d_107 = dummy_s;
@@ -5575,11 +5575,11 @@ end
 reg dummy_d_108;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_master_p0_wrdata_mask <= 8'd0;
+       soc_litedramcore_master_p3_reset_n <= 1'd0;
        if (soc_litedramcore_sel) begin
-               soc_litedramcore_master_p0_wrdata_mask <= soc_litedramcore_slave_p0_wrdata_mask;
+               soc_litedramcore_master_p3_reset_n <= soc_litedramcore_slave_p3_reset_n;
        end else begin
-               soc_litedramcore_master_p0_wrdata_mask <= soc_litedramcore_inti_p0_wrdata_mask;
+               soc_litedramcore_master_p3_reset_n <= soc_litedramcore_inti_p3_reset_n;
        end
 // synthesis translate_off
        dummy_d_108 = dummy_s;
@@ -5590,11 +5590,11 @@ end
 reg dummy_d_109;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_master_p0_rddata_en <= 1'd0;
+       soc_litedramcore_master_p3_act_n <= 1'd1;
        if (soc_litedramcore_sel) begin
-               soc_litedramcore_master_p0_rddata_en <= soc_litedramcore_slave_p0_rddata_en;
+               soc_litedramcore_master_p3_act_n <= soc_litedramcore_slave_p3_act_n;
        end else begin
-               soc_litedramcore_master_p0_rddata_en <= soc_litedramcore_inti_p0_rddata_en;
+               soc_litedramcore_master_p3_act_n <= soc_litedramcore_inti_p3_act_n;
        end
 // synthesis translate_off
        dummy_d_109 = dummy_s;
@@ -5605,11 +5605,11 @@ end
 reg dummy_d_110;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_master_p1_address <= 15'd0;
+       soc_litedramcore_master_p3_wrdata <= 64'd0;
        if (soc_litedramcore_sel) begin
-               soc_litedramcore_master_p1_address <= soc_litedramcore_slave_p1_address;
+               soc_litedramcore_master_p3_wrdata <= soc_litedramcore_slave_p3_wrdata;
        end else begin
-               soc_litedramcore_master_p1_address <= soc_litedramcore_inti_p1_address;
+               soc_litedramcore_master_p3_wrdata <= soc_litedramcore_inti_p3_wrdata;
        end
 // synthesis translate_off
        dummy_d_110 = dummy_s;
@@ -5620,11 +5620,11 @@ end
 reg dummy_d_111;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_master_p1_bank <= 3'd0;
+       soc_litedramcore_master_p3_wrdata_en <= 1'd0;
        if (soc_litedramcore_sel) begin
-               soc_litedramcore_master_p1_bank <= soc_litedramcore_slave_p1_bank;
+               soc_litedramcore_master_p3_wrdata_en <= soc_litedramcore_slave_p3_wrdata_en;
        end else begin
-               soc_litedramcore_master_p1_bank <= soc_litedramcore_inti_p1_bank;
+               soc_litedramcore_master_p3_wrdata_en <= soc_litedramcore_inti_p3_wrdata_en;
        end
 // synthesis translate_off
        dummy_d_111 = dummy_s;
@@ -5635,11 +5635,11 @@ end
 reg dummy_d_112;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_master_p1_cas_n <= 1'd1;
+       soc_litedramcore_master_p3_wrdata_mask <= 8'd0;
        if (soc_litedramcore_sel) begin
-               soc_litedramcore_master_p1_cas_n <= soc_litedramcore_slave_p1_cas_n;
+               soc_litedramcore_master_p3_wrdata_mask <= soc_litedramcore_slave_p3_wrdata_mask;
        end else begin
-               soc_litedramcore_master_p1_cas_n <= soc_litedramcore_inti_p1_cas_n;
+               soc_litedramcore_master_p3_wrdata_mask <= soc_litedramcore_inti_p3_wrdata_mask;
        end
 // synthesis translate_off
        dummy_d_112 = dummy_s;
@@ -5650,11 +5650,11 @@ end
 reg dummy_d_113;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_master_p1_cs_n <= 1'd1;
+       soc_litedramcore_master_p3_rddata_en <= 1'd0;
        if (soc_litedramcore_sel) begin
-               soc_litedramcore_master_p1_cs_n <= soc_litedramcore_slave_p1_cs_n;
+               soc_litedramcore_master_p3_rddata_en <= soc_litedramcore_slave_p3_rddata_en;
        end else begin
-               soc_litedramcore_master_p1_cs_n <= soc_litedramcore_inti_p1_cs_n;
+               soc_litedramcore_master_p3_rddata_en <= soc_litedramcore_inti_p3_rddata_en;
        end
 // synthesis translate_off
        dummy_d_113 = dummy_s;
@@ -5677,11 +5677,11 @@ assign soc_litedramcore_inti_p3_reset_n = soc_litedramcore_reset_n;
 reg dummy_d_114;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_inti_p0_ras_n <= 1'd1;
+       soc_litedramcore_inti_p0_cs_n <= 1'd1;
        if (soc_litedramcore_phaseinjector0_command_issue_re) begin
-               soc_litedramcore_inti_p0_ras_n <= (~soc_litedramcore_phaseinjector0_command_storage[3]);
+               soc_litedramcore_inti_p0_cs_n <= {1{(~soc_litedramcore_phaseinjector0_command_storage[0])}};
        end else begin
-               soc_litedramcore_inti_p0_ras_n <= 1'd1;
+               soc_litedramcore_inti_p0_cs_n <= {1{1'd1}};
        end
 // synthesis translate_off
        dummy_d_114 = dummy_s;
@@ -5692,11 +5692,11 @@ end
 reg dummy_d_115;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_inti_p0_we_n <= 1'd1;
+       soc_litedramcore_inti_p0_ras_n <= 1'd1;
        if (soc_litedramcore_phaseinjector0_command_issue_re) begin
-               soc_litedramcore_inti_p0_we_n <= (~soc_litedramcore_phaseinjector0_command_storage[1]);
+               soc_litedramcore_inti_p0_ras_n <= (~soc_litedramcore_phaseinjector0_command_storage[3]);
        end else begin
-               soc_litedramcore_inti_p0_we_n <= 1'd1;
+               soc_litedramcore_inti_p0_ras_n <= 1'd1;
        end
 // synthesis translate_off
        dummy_d_115 = dummy_s;
@@ -5707,11 +5707,11 @@ end
 reg dummy_d_116;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_inti_p0_cas_n <= 1'd1;
+       soc_litedramcore_inti_p0_we_n <= 1'd1;
        if (soc_litedramcore_phaseinjector0_command_issue_re) begin
-               soc_litedramcore_inti_p0_cas_n <= (~soc_litedramcore_phaseinjector0_command_storage[2]);
+               soc_litedramcore_inti_p0_we_n <= (~soc_litedramcore_phaseinjector0_command_storage[1]);
        end else begin
-               soc_litedramcore_inti_p0_cas_n <= 1'd1;
+               soc_litedramcore_inti_p0_we_n <= 1'd1;
        end
 // synthesis translate_off
        dummy_d_116 = dummy_s;
@@ -5722,11 +5722,11 @@ end
 reg dummy_d_117;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_inti_p0_cs_n <= 1'd1;
+       soc_litedramcore_inti_p0_cas_n <= 1'd1;
        if (soc_litedramcore_phaseinjector0_command_issue_re) begin
-               soc_litedramcore_inti_p0_cs_n <= {1{(~soc_litedramcore_phaseinjector0_command_storage[0])}};
+               soc_litedramcore_inti_p0_cas_n <= (~soc_litedramcore_phaseinjector0_command_storage[2]);
        end else begin
-               soc_litedramcore_inti_p0_cs_n <= {1{1'd1}};
+               soc_litedramcore_inti_p0_cas_n <= 1'd1;
        end
 // synthesis translate_off
        dummy_d_117 = dummy_s;
@@ -5743,11 +5743,11 @@ assign soc_litedramcore_inti_p0_wrdata_mask = 1'd0;
 reg dummy_d_118;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_inti_p1_ras_n <= 1'd1;
+       soc_litedramcore_inti_p1_cs_n <= 1'd1;
        if (soc_litedramcore_phaseinjector1_command_issue_re) begin
-               soc_litedramcore_inti_p1_ras_n <= (~soc_litedramcore_phaseinjector1_command_storage[3]);
+               soc_litedramcore_inti_p1_cs_n <= {1{(~soc_litedramcore_phaseinjector1_command_storage[0])}};
        end else begin
-               soc_litedramcore_inti_p1_ras_n <= 1'd1;
+               soc_litedramcore_inti_p1_cs_n <= {1{1'd1}};
        end
 // synthesis translate_off
        dummy_d_118 = dummy_s;
@@ -5758,11 +5758,11 @@ end
 reg dummy_d_119;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_inti_p1_we_n <= 1'd1;
+       soc_litedramcore_inti_p1_ras_n <= 1'd1;
        if (soc_litedramcore_phaseinjector1_command_issue_re) begin
-               soc_litedramcore_inti_p1_we_n <= (~soc_litedramcore_phaseinjector1_command_storage[1]);
+               soc_litedramcore_inti_p1_ras_n <= (~soc_litedramcore_phaseinjector1_command_storage[3]);
        end else begin
-               soc_litedramcore_inti_p1_we_n <= 1'd1;
+               soc_litedramcore_inti_p1_ras_n <= 1'd1;
        end
 // synthesis translate_off
        dummy_d_119 = dummy_s;
@@ -5773,11 +5773,11 @@ end
 reg dummy_d_120;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_inti_p1_cas_n <= 1'd1;
+       soc_litedramcore_inti_p1_we_n <= 1'd1;
        if (soc_litedramcore_phaseinjector1_command_issue_re) begin
-               soc_litedramcore_inti_p1_cas_n <= (~soc_litedramcore_phaseinjector1_command_storage[2]);
+               soc_litedramcore_inti_p1_we_n <= (~soc_litedramcore_phaseinjector1_command_storage[1]);
        end else begin
-               soc_litedramcore_inti_p1_cas_n <= 1'd1;
+               soc_litedramcore_inti_p1_we_n <= 1'd1;
        end
 // synthesis translate_off
        dummy_d_120 = dummy_s;
@@ -5788,11 +5788,11 @@ end
 reg dummy_d_121;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_inti_p1_cs_n <= 1'd1;
+       soc_litedramcore_inti_p1_cas_n <= 1'd1;
        if (soc_litedramcore_phaseinjector1_command_issue_re) begin
-               soc_litedramcore_inti_p1_cs_n <= {1{(~soc_litedramcore_phaseinjector1_command_storage[0])}};
+               soc_litedramcore_inti_p1_cas_n <= (~soc_litedramcore_phaseinjector1_command_storage[2]);
        end else begin
-               soc_litedramcore_inti_p1_cs_n <= {1{1'd1}};
+               soc_litedramcore_inti_p1_cas_n <= 1'd1;
        end
 // synthesis translate_off
        dummy_d_121 = dummy_s;
@@ -5809,11 +5809,11 @@ assign soc_litedramcore_inti_p1_wrdata_mask = 1'd0;
 reg dummy_d_122;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_inti_p2_ras_n <= 1'd1;
+       soc_litedramcore_inti_p2_cs_n <= 1'd1;
        if (soc_litedramcore_phaseinjector2_command_issue_re) begin
-               soc_litedramcore_inti_p2_ras_n <= (~soc_litedramcore_phaseinjector2_command_storage[3]);
+               soc_litedramcore_inti_p2_cs_n <= {1{(~soc_litedramcore_phaseinjector2_command_storage[0])}};
        end else begin
-               soc_litedramcore_inti_p2_ras_n <= 1'd1;
+               soc_litedramcore_inti_p2_cs_n <= {1{1'd1}};
        end
 // synthesis translate_off
        dummy_d_122 = dummy_s;
@@ -5824,11 +5824,11 @@ end
 reg dummy_d_123;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_inti_p2_we_n <= 1'd1;
+       soc_litedramcore_inti_p2_ras_n <= 1'd1;
        if (soc_litedramcore_phaseinjector2_command_issue_re) begin
-               soc_litedramcore_inti_p2_we_n <= (~soc_litedramcore_phaseinjector2_command_storage[1]);
+               soc_litedramcore_inti_p2_ras_n <= (~soc_litedramcore_phaseinjector2_command_storage[3]);
        end else begin
-               soc_litedramcore_inti_p2_we_n <= 1'd1;
+               soc_litedramcore_inti_p2_ras_n <= 1'd1;
        end
 // synthesis translate_off
        dummy_d_123 = dummy_s;
@@ -5839,11 +5839,11 @@ end
 reg dummy_d_124;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_inti_p2_cas_n <= 1'd1;
+       soc_litedramcore_inti_p2_we_n <= 1'd1;
        if (soc_litedramcore_phaseinjector2_command_issue_re) begin
-               soc_litedramcore_inti_p2_cas_n <= (~soc_litedramcore_phaseinjector2_command_storage[2]);
+               soc_litedramcore_inti_p2_we_n <= (~soc_litedramcore_phaseinjector2_command_storage[1]);
        end else begin
-               soc_litedramcore_inti_p2_cas_n <= 1'd1;
+               soc_litedramcore_inti_p2_we_n <= 1'd1;
        end
 // synthesis translate_off
        dummy_d_124 = dummy_s;
@@ -5854,11 +5854,11 @@ end
 reg dummy_d_125;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_inti_p2_cs_n <= 1'd1;
+       soc_litedramcore_inti_p2_cas_n <= 1'd1;
        if (soc_litedramcore_phaseinjector2_command_issue_re) begin
-               soc_litedramcore_inti_p2_cs_n <= {1{(~soc_litedramcore_phaseinjector2_command_storage[0])}};
+               soc_litedramcore_inti_p2_cas_n <= (~soc_litedramcore_phaseinjector2_command_storage[2]);
        end else begin
-               soc_litedramcore_inti_p2_cs_n <= {1{1'd1}};
+               soc_litedramcore_inti_p2_cas_n <= 1'd1;
        end
 // synthesis translate_off
        dummy_d_125 = dummy_s;
@@ -5875,11 +5875,11 @@ assign soc_litedramcore_inti_p2_wrdata_mask = 1'd0;
 reg dummy_d_126;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_inti_p3_ras_n <= 1'd1;
+       soc_litedramcore_inti_p3_cs_n <= 1'd1;
        if (soc_litedramcore_phaseinjector3_command_issue_re) begin
-               soc_litedramcore_inti_p3_ras_n <= (~soc_litedramcore_phaseinjector3_command_storage[3]);
+               soc_litedramcore_inti_p3_cs_n <= {1{(~soc_litedramcore_phaseinjector3_command_storage[0])}};
        end else begin
-               soc_litedramcore_inti_p3_ras_n <= 1'd1;
+               soc_litedramcore_inti_p3_cs_n <= {1{1'd1}};
        end
 // synthesis translate_off
        dummy_d_126 = dummy_s;
@@ -5890,11 +5890,11 @@ end
 reg dummy_d_127;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_inti_p3_we_n <= 1'd1;
+       soc_litedramcore_inti_p3_ras_n <= 1'd1;
        if (soc_litedramcore_phaseinjector3_command_issue_re) begin
-               soc_litedramcore_inti_p3_we_n <= (~soc_litedramcore_phaseinjector3_command_storage[1]);
+               soc_litedramcore_inti_p3_ras_n <= (~soc_litedramcore_phaseinjector3_command_storage[3]);
        end else begin
-               soc_litedramcore_inti_p3_we_n <= 1'd1;
+               soc_litedramcore_inti_p3_ras_n <= 1'd1;
        end
 // synthesis translate_off
        dummy_d_127 = dummy_s;
@@ -5905,11 +5905,11 @@ end
 reg dummy_d_128;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_inti_p3_cas_n <= 1'd1;
+       soc_litedramcore_inti_p3_we_n <= 1'd1;
        if (soc_litedramcore_phaseinjector3_command_issue_re) begin
-               soc_litedramcore_inti_p3_cas_n <= (~soc_litedramcore_phaseinjector3_command_storage[2]);
+               soc_litedramcore_inti_p3_we_n <= (~soc_litedramcore_phaseinjector3_command_storage[1]);
        end else begin
-               soc_litedramcore_inti_p3_cas_n <= 1'd1;
+               soc_litedramcore_inti_p3_we_n <= 1'd1;
        end
 // synthesis translate_off
        dummy_d_128 = dummy_s;
@@ -5920,11 +5920,11 @@ end
 reg dummy_d_129;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_inti_p3_cs_n <= 1'd1;
+       soc_litedramcore_inti_p3_cas_n <= 1'd1;
        if (soc_litedramcore_phaseinjector3_command_issue_re) begin
-               soc_litedramcore_inti_p3_cs_n <= {1{(~soc_litedramcore_phaseinjector3_command_storage[0])}};
+               soc_litedramcore_inti_p3_cas_n <= (~soc_litedramcore_phaseinjector3_command_storage[2]);
        end else begin
-               soc_litedramcore_inti_p3_cs_n <= {1{1'd1}};
+               soc_litedramcore_inti_p3_cas_n <= 1'd1;
        end
 // synthesis translate_off
        dummy_d_129 = dummy_s;
@@ -6049,25 +6049,16 @@ end
 reg dummy_d_131;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_cmd_valid <= 1'd0;
+       soc_litedramcore_sequencer_start0 <= 1'd0;
        case (vns_refresher_state)
                1'd1: begin
-                       soc_litedramcore_cmd_valid <= 1'd1;
+                       if (soc_litedramcore_cmd_ready) begin
+                               soc_litedramcore_sequencer_start0 <= 1'd1;
+                       end
                end
                2'd2: begin
-                       soc_litedramcore_cmd_valid <= 1'd1;
-                       if (soc_litedramcore_sequencer_done0) begin
-                               if (soc_litedramcore_wants_zqcs) begin
-                               end else begin
-                                       soc_litedramcore_cmd_valid <= 1'd0;
-                               end
-                       end
                end
                2'd3: begin
-                       soc_litedramcore_cmd_valid <= 1'd1;
-                       if (soc_litedramcore_zqcs_executer_done) begin
-                               soc_litedramcore_cmd_valid <= 1'd0;
-                       end
                end
                default: begin
                end
@@ -6081,19 +6072,25 @@ end
 reg dummy_d_132;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_zqcs_executer_start <= 1'd0;
+       soc_litedramcore_cmd_valid <= 1'd0;
        case (vns_refresher_state)
                1'd1: begin
+                       soc_litedramcore_cmd_valid <= 1'd1;
                end
                2'd2: begin
+                       soc_litedramcore_cmd_valid <= 1'd1;
                        if (soc_litedramcore_sequencer_done0) begin
                                if (soc_litedramcore_wants_zqcs) begin
-                                       soc_litedramcore_zqcs_executer_start <= 1'd1;
                                end else begin
+                                       soc_litedramcore_cmd_valid <= 1'd0;
                                end
                        end
                end
                2'd3: begin
+                       soc_litedramcore_cmd_valid <= 1'd1;
+                       if (soc_litedramcore_zqcs_executer_done) begin
+                               soc_litedramcore_cmd_valid <= 1'd0;
+                       end
                end
                default: begin
                end
@@ -6107,22 +6104,19 @@ end
 reg dummy_d_133;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_cmd_last <= 1'd0;
+       soc_litedramcore_zqcs_executer_start <= 1'd0;
        case (vns_refresher_state)
                1'd1: begin
                end
                2'd2: begin
                        if (soc_litedramcore_sequencer_done0) begin
                                if (soc_litedramcore_wants_zqcs) begin
+                                       soc_litedramcore_zqcs_executer_start <= 1'd1;
                                end else begin
-                                       soc_litedramcore_cmd_last <= 1'd1;
                                end
                        end
                end
                2'd3: begin
-                       if (soc_litedramcore_zqcs_executer_done) begin
-                               soc_litedramcore_cmd_last <= 1'd1;
-                       end
                end
                default: begin
                end
@@ -6136,16 +6130,22 @@ end
 reg dummy_d_134;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_sequencer_start0 <= 1'd0;
+       soc_litedramcore_cmd_last <= 1'd0;
        case (vns_refresher_state)
                1'd1: begin
-                       if (soc_litedramcore_cmd_ready) begin
-                               soc_litedramcore_sequencer_start0 <= 1'd1;
-                       end
                end
                2'd2: begin
+                       if (soc_litedramcore_sequencer_done0) begin
+                               if (soc_litedramcore_wants_zqcs) begin
+                               end else begin
+                                       soc_litedramcore_cmd_last <= 1'd1;
+                               end
+                       end
                end
                2'd3: begin
+                       if (soc_litedramcore_zqcs_executer_done) begin
+                               soc_litedramcore_cmd_last <= 1'd1;
+                       end
                end
                default: begin
                end
@@ -6314,7 +6314,7 @@ end
 reg dummy_d_139;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_bankmachine0_cmd_payload_is_write <= 1'd0;
+       soc_litedramcore_bankmachine0_cmd_payload_cas <= 1'd0;
        case (vns_bankmachine0_state)
                1'd1: begin
                end
@@ -6338,10 +6338,7 @@ always @(*) begin
                                if (soc_litedramcore_bankmachine0_cmd_buffer_source_valid) begin
                                        if (soc_litedramcore_bankmachine0_row_opened) begin
                                                if (soc_litedramcore_bankmachine0_row_hit) begin
-                                                       if (soc_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
-                                                               soc_litedramcore_bankmachine0_cmd_payload_is_write <= 1'd1;
-                                                       end else begin
-                                                       end
+                                                       soc_litedramcore_bankmachine0_cmd_payload_cas <= 1'd1;
                                                end else begin
                                                end
                                        end else begin
@@ -6359,41 +6356,32 @@ end
 reg dummy_d_140;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_bankmachine0_req_wdata_ready <= 1'd0;
+       soc_litedramcore_bankmachine0_cmd_payload_ras <= 1'd0;
        case (vns_bankmachine0_state)
                1'd1: begin
+                       if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin
+                               soc_litedramcore_bankmachine0_cmd_payload_ras <= 1'd1;
+                       end
                end
                2'd2: begin
                end
                2'd3: begin
-               end
-               3'd4: begin
-               end
-               3'd5: begin
-               end
-               3'd6: begin
-               end
-               3'd7: begin
-               end
-               4'd8: begin
-               end
-               default: begin
-                       if (soc_litedramcore_bankmachine0_refresh_req) begin
-                       end else begin
-                               if (soc_litedramcore_bankmachine0_cmd_buffer_source_valid) begin
-                                       if (soc_litedramcore_bankmachine0_row_opened) begin
-                                               if (soc_litedramcore_bankmachine0_row_hit) begin
-                                                       if (soc_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
-                                                               soc_litedramcore_bankmachine0_req_wdata_ready <= soc_litedramcore_bankmachine0_cmd_ready;
-                                                       end else begin
-                                                       end
-                                               end else begin
-                                               end
-                                       end else begin
-                                       end
-                               end
+                       if (soc_litedramcore_bankmachine0_trccon_ready) begin
+                               soc_litedramcore_bankmachine0_cmd_payload_ras <= 1'd1;
                        end
                end
+               3'd4: begin
+               end
+               3'd5: begin
+               end
+               3'd6: begin
+               end
+               3'd7: begin
+               end
+               4'd8: begin
+               end
+               default: begin
+               end
        endcase
 // synthesis translate_off
        dummy_d_140 = dummy_s;
@@ -6404,9 +6392,12 @@ end
 reg dummy_d_141;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_bankmachine0_req_rdata_valid <= 1'd0;
+       soc_litedramcore_bankmachine0_cmd_payload_we <= 1'd0;
        case (vns_bankmachine0_state)
                1'd1: begin
+                       if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin
+                               soc_litedramcore_bankmachine0_cmd_payload_we <= 1'd1;
+                       end
                end
                2'd2: begin
                end
@@ -6429,8 +6420,8 @@ always @(*) begin
                                        if (soc_litedramcore_bankmachine0_row_opened) begin
                                                if (soc_litedramcore_bankmachine0_row_hit) begin
                                                        if (soc_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
+                                                               soc_litedramcore_bankmachine0_cmd_payload_we <= 1'd1;
                                                        end else begin
-                                                               soc_litedramcore_bankmachine0_req_rdata_valid <= soc_litedramcore_bankmachine0_cmd_ready;
                                                        end
                                                end else begin
                                                end
@@ -6449,18 +6440,18 @@ end
 reg dummy_d_142;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_bankmachine0_refresh_gnt <= 1'd0;
+       soc_litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0;
        case (vns_bankmachine0_state)
                1'd1: begin
                end
                2'd2: begin
                end
                2'd3: begin
+                       if (soc_litedramcore_bankmachine0_trccon_ready) begin
+                               soc_litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd1;
+                       end
                end
                3'd4: begin
-                       if (soc_litedramcore_bankmachine0_twtpcon_ready) begin
-                               soc_litedramcore_bankmachine0_refresh_gnt <= 1'd1;
-                       end
                end
                3'd5: begin
                end
@@ -6482,21 +6473,22 @@ end
 reg dummy_d_143;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_bankmachine0_cmd_valid <= 1'd0;
+       soc_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd0;
        case (vns_bankmachine0_state)
                1'd1: begin
                        if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin
-                               soc_litedramcore_bankmachine0_cmd_valid <= 1'd1;
+                               soc_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
                        end
                end
                2'd2: begin
                end
                2'd3: begin
                        if (soc_litedramcore_bankmachine0_trccon_ready) begin
-                               soc_litedramcore_bankmachine0_cmd_valid <= 1'd1;
+                               soc_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
                        end
                end
                3'd4: begin
+                       soc_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
                end
                3'd5: begin
                end
@@ -6507,18 +6499,6 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
-                       if (soc_litedramcore_bankmachine0_refresh_req) begin
-                       end else begin
-                               if (soc_litedramcore_bankmachine0_cmd_buffer_source_valid) begin
-                                       if (soc_litedramcore_bankmachine0_row_opened) begin
-                                               if (soc_litedramcore_bankmachine0_row_hit) begin
-                                                       soc_litedramcore_bankmachine0_cmd_valid <= 1'd1;
-                                               end else begin
-                                               end
-                                       end else begin
-                                       end
-                               end
-                       end
                end
        endcase
 // synthesis translate_off
@@ -6530,16 +6510,13 @@ end
 reg dummy_d_144;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_bankmachine0_row_open <= 1'd0;
+       soc_litedramcore_bankmachine0_cmd_payload_is_read <= 1'd0;
        case (vns_bankmachine0_state)
                1'd1: begin
                end
                2'd2: begin
                end
                2'd3: begin
-                       if (soc_litedramcore_bankmachine0_trccon_ready) begin
-                               soc_litedramcore_bankmachine0_row_open <= 1'd1;
-                       end
                end
                3'd4: begin
                end
@@ -6552,6 +6529,21 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
+                       if (soc_litedramcore_bankmachine0_refresh_req) begin
+                       end else begin
+                               if (soc_litedramcore_bankmachine0_cmd_buffer_source_valid) begin
+                                       if (soc_litedramcore_bankmachine0_row_opened) begin
+                                               if (soc_litedramcore_bankmachine0_row_hit) begin
+                                                       if (soc_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
+                                                       end else begin
+                                                               soc_litedramcore_bankmachine0_cmd_payload_is_read <= 1'd1;
+                                                       end
+                                               end else begin
+                                               end
+                                       end else begin
+                                       end
+                               end
+                       end
                end
        endcase
 // synthesis translate_off
@@ -6563,18 +6555,15 @@ end
 reg dummy_d_145;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_bankmachine0_row_close <= 1'd0;
+       soc_litedramcore_bankmachine0_cmd_payload_is_write <= 1'd0;
        case (vns_bankmachine0_state)
                1'd1: begin
-                       soc_litedramcore_bankmachine0_row_close <= 1'd1;
                end
                2'd2: begin
-                       soc_litedramcore_bankmachine0_row_close <= 1'd1;
                end
                2'd3: begin
                end
                3'd4: begin
-                       soc_litedramcore_bankmachine0_row_close <= 1'd1;
                end
                3'd5: begin
                end
@@ -6585,6 +6574,21 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
+                       if (soc_litedramcore_bankmachine0_refresh_req) begin
+                       end else begin
+                               if (soc_litedramcore_bankmachine0_cmd_buffer_source_valid) begin
+                                       if (soc_litedramcore_bankmachine0_row_opened) begin
+                                               if (soc_litedramcore_bankmachine0_row_hit) begin
+                                                       if (soc_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
+                                                               soc_litedramcore_bankmachine0_cmd_payload_is_write <= 1'd1;
+                                                       end else begin
+                                                       end
+                                               end else begin
+                                               end
+                                       end else begin
+                                       end
+                               end
+                       end
                end
        endcase
 // synthesis translate_off
@@ -6596,7 +6600,7 @@ end
 reg dummy_d_146;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_bankmachine0_cmd_payload_cas <= 1'd0;
+       soc_litedramcore_bankmachine0_req_wdata_ready <= 1'd0;
        case (vns_bankmachine0_state)
                1'd1: begin
                end
@@ -6620,7 +6624,10 @@ always @(*) begin
                                if (soc_litedramcore_bankmachine0_cmd_buffer_source_valid) begin
                                        if (soc_litedramcore_bankmachine0_row_opened) begin
                                                if (soc_litedramcore_bankmachine0_row_hit) begin
-                                                       soc_litedramcore_bankmachine0_cmd_payload_cas <= 1'd1;
+                                                       if (soc_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
+                                                               soc_litedramcore_bankmachine0_req_wdata_ready <= soc_litedramcore_bankmachine0_cmd_ready;
+                                                       end else begin
+                                                       end
                                                end else begin
                                                end
                                        end else begin
@@ -6638,19 +6645,13 @@ end
 reg dummy_d_147;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_bankmachine0_cmd_payload_ras <= 1'd0;
+       soc_litedramcore_bankmachine0_req_rdata_valid <= 1'd0;
        case (vns_bankmachine0_state)
                1'd1: begin
-                       if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin
-                               soc_litedramcore_bankmachine0_cmd_payload_ras <= 1'd1;
-                       end
                end
                2'd2: begin
                end
                2'd3: begin
-                       if (soc_litedramcore_bankmachine0_trccon_ready) begin
-                               soc_litedramcore_bankmachine0_cmd_payload_ras <= 1'd1;
-                       end
                end
                3'd4: begin
                end
@@ -6663,6 +6664,21 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
+                       if (soc_litedramcore_bankmachine0_refresh_req) begin
+                       end else begin
+                               if (soc_litedramcore_bankmachine0_cmd_buffer_source_valid) begin
+                                       if (soc_litedramcore_bankmachine0_row_opened) begin
+                                               if (soc_litedramcore_bankmachine0_row_hit) begin
+                                                       if (soc_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
+                                                       end else begin
+                                                               soc_litedramcore_bankmachine0_req_rdata_valid <= soc_litedramcore_bankmachine0_cmd_ready;
+                                                       end
+                                               end else begin
+                                               end
+                                       end else begin
+                                       end
+                               end
+                       end
                end
        endcase
 // synthesis translate_off
@@ -6674,18 +6690,18 @@ end
 reg dummy_d_148;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd0;
+       soc_litedramcore_bankmachine0_refresh_gnt <= 1'd0;
        case (vns_bankmachine0_state)
                1'd1: begin
                end
                2'd2: begin
                end
                2'd3: begin
-                       if (soc_litedramcore_bankmachine0_trccon_ready) begin
-                               soc_litedramcore_bankmachine0_row_col_n_addr_sel <= 1'd1;
-                       end
                end
                3'd4: begin
+                       if (soc_litedramcore_bankmachine0_twtpcon_ready) begin
+                               soc_litedramcore_bankmachine0_refresh_gnt <= 1'd1;
+                       end
                end
                3'd5: begin
                end
@@ -6707,16 +6723,19 @@ end
 reg dummy_d_149;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_bankmachine0_cmd_payload_we <= 1'd0;
+       soc_litedramcore_bankmachine0_cmd_valid <= 1'd0;
        case (vns_bankmachine0_state)
                1'd1: begin
                        if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin
-                               soc_litedramcore_bankmachine0_cmd_payload_we <= 1'd1;
+                               soc_litedramcore_bankmachine0_cmd_valid <= 1'd1;
                        end
                end
                2'd2: begin
                end
                2'd3: begin
+                       if (soc_litedramcore_bankmachine0_trccon_ready) begin
+                               soc_litedramcore_bankmachine0_cmd_valid <= 1'd1;
+                       end
                end
                3'd4: begin
                end
@@ -6734,10 +6753,7 @@ always @(*) begin
                                if (soc_litedramcore_bankmachine0_cmd_buffer_source_valid) begin
                                        if (soc_litedramcore_bankmachine0_row_opened) begin
                                                if (soc_litedramcore_bankmachine0_row_hit) begin
-                                                       if (soc_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
-                                                               soc_litedramcore_bankmachine0_cmd_payload_we <= 1'd1;
-                                                       end else begin
-                                                       end
+                                                       soc_litedramcore_bankmachine0_cmd_valid <= 1'd1;
                                                end else begin
                                                end
                                        end else begin
@@ -6755,22 +6771,18 @@ end
 reg dummy_d_150;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd0;
+       soc_litedramcore_bankmachine0_row_open <= 1'd0;
        case (vns_bankmachine0_state)
                1'd1: begin
-                       if ((soc_litedramcore_bankmachine0_twtpcon_ready & soc_litedramcore_bankmachine0_trascon_ready)) begin
-                               soc_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
-                       end
                end
                2'd2: begin
                end
                2'd3: begin
                        if (soc_litedramcore_bankmachine0_trccon_ready) begin
-                               soc_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
+                               soc_litedramcore_bankmachine0_row_open <= 1'd1;
                        end
                end
                3'd4: begin
-                       soc_litedramcore_bankmachine0_cmd_payload_is_cmd <= 1'd1;
                end
                3'd5: begin
                end
@@ -6792,15 +6804,18 @@ end
 reg dummy_d_151;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_bankmachine0_cmd_payload_is_read <= 1'd0;
+       soc_litedramcore_bankmachine0_row_close <= 1'd0;
        case (vns_bankmachine0_state)
                1'd1: begin
+                       soc_litedramcore_bankmachine0_row_close <= 1'd1;
                end
                2'd2: begin
+                       soc_litedramcore_bankmachine0_row_close <= 1'd1;
                end
                2'd3: begin
                end
                3'd4: begin
+                       soc_litedramcore_bankmachine0_row_close <= 1'd1;
                end
                3'd5: begin
                end
@@ -6811,21 +6826,6 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
-                       if (soc_litedramcore_bankmachine0_refresh_req) begin
-                       end else begin
-                               if (soc_litedramcore_bankmachine0_cmd_buffer_source_valid) begin
-                                       if (soc_litedramcore_bankmachine0_row_opened) begin
-                                               if (soc_litedramcore_bankmachine0_row_hit) begin
-                                                       if (soc_litedramcore_bankmachine0_cmd_buffer_source_payload_we) begin
-                                                       end else begin
-                                                               soc_litedramcore_bankmachine0_cmd_payload_is_read <= 1'd1;
-                                                       end
-                                               end else begin
-                                               end
-                                       end else begin
-                                       end
-                               end
-                       end
                end
        endcase
 // synthesis translate_off
@@ -6992,7 +6992,7 @@ end
 reg dummy_d_156;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_bankmachine1_cmd_payload_is_write <= 1'd0;
+       soc_litedramcore_bankmachine1_cmd_payload_cas <= 1'd0;
        case (vns_bankmachine1_state)
                1'd1: begin
                end
@@ -7016,10 +7016,7 @@ always @(*) begin
                                if (soc_litedramcore_bankmachine1_cmd_buffer_source_valid) begin
                                        if (soc_litedramcore_bankmachine1_row_opened) begin
                                                if (soc_litedramcore_bankmachine1_row_hit) begin
-                                                       if (soc_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
-                                                               soc_litedramcore_bankmachine1_cmd_payload_is_write <= 1'd1;
-                                                       end else begin
-                                                       end
+                                                       soc_litedramcore_bankmachine1_cmd_payload_cas <= 1'd1;
                                                end else begin
                                                end
                                        end else begin
@@ -7037,13 +7034,19 @@ end
 reg dummy_d_157;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_bankmachine1_req_wdata_ready <= 1'd0;
+       soc_litedramcore_bankmachine1_cmd_payload_ras <= 1'd0;
        case (vns_bankmachine1_state)
                1'd1: begin
+                       if ((soc_litedramcore_bankmachine1_twtpcon_ready & soc_litedramcore_bankmachine1_trascon_ready)) begin
+                               soc_litedramcore_bankmachine1_cmd_payload_ras <= 1'd1;
+                       end
                end
                2'd2: begin
                end
                2'd3: begin
+                       if (soc_litedramcore_bankmachine1_trccon_ready) begin
+                               soc_litedramcore_bankmachine1_cmd_payload_ras <= 1'd1;
+                       end
                end
                3'd4: begin
                end
@@ -7056,21 +7059,6 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
-                       if (soc_litedramcore_bankmachine1_refresh_req) begin
-                       end else begin
-                               if (soc_litedramcore_bankmachine1_cmd_buffer_source_valid) begin
-                                       if (soc_litedramcore_bankmachine1_row_opened) begin
-                                               if (soc_litedramcore_bankmachine1_row_hit) begin
-                                                       if (soc_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
-                                                               soc_litedramcore_bankmachine1_req_wdata_ready <= soc_litedramcore_bankmachine1_cmd_ready;
-                                                       end else begin
-                                                       end
-                                               end else begin
-                                               end
-                                       end else begin
-                                       end
-                               end
-                       end
                end
        endcase
 // synthesis translate_off
@@ -7082,16 +7070,16 @@ end
 reg dummy_d_158;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0;
+       soc_litedramcore_bankmachine1_cmd_payload_we <= 1'd0;
        case (vns_bankmachine1_state)
                1'd1: begin
+                       if ((soc_litedramcore_bankmachine1_twtpcon_ready & soc_litedramcore_bankmachine1_trascon_ready)) begin
+                               soc_litedramcore_bankmachine1_cmd_payload_we <= 1'd1;
+                       end
                end
                2'd2: begin
                end
                2'd3: begin
-                       if (soc_litedramcore_bankmachine1_trccon_ready) begin
-                               soc_litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd1;
-                       end
                end
                3'd4: begin
                end
@@ -7104,6 +7092,21 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
+                       if (soc_litedramcore_bankmachine1_refresh_req) begin
+                       end else begin
+                               if (soc_litedramcore_bankmachine1_cmd_buffer_source_valid) begin
+                                       if (soc_litedramcore_bankmachine1_row_opened) begin
+                                               if (soc_litedramcore_bankmachine1_row_hit) begin
+                                                       if (soc_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
+                                                               soc_litedramcore_bankmachine1_cmd_payload_we <= 1'd1;
+                                                       end else begin
+                                                       end
+                                               end else begin
+                                               end
+                                       end else begin
+                                       end
+                               end
+                       end
                end
        endcase
 // synthesis translate_off
@@ -7115,13 +7118,16 @@ end
 reg dummy_d_159;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_bankmachine1_req_rdata_valid <= 1'd0;
+       soc_litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd0;
        case (vns_bankmachine1_state)
                1'd1: begin
                end
                2'd2: begin
                end
                2'd3: begin
+                       if (soc_litedramcore_bankmachine1_trccon_ready) begin
+                               soc_litedramcore_bankmachine1_row_col_n_addr_sel <= 1'd1;
+                       end
                end
                3'd4: begin
                end
@@ -7134,21 +7140,6 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
-                       if (soc_litedramcore_bankmachine1_refresh_req) begin
-                       end else begin
-                               if (soc_litedramcore_bankmachine1_cmd_buffer_source_valid) begin
-                                       if (soc_litedramcore_bankmachine1_row_opened) begin
-                                               if (soc_litedramcore_bankmachine1_row_hit) begin
-                                                       if (soc_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
-                                                       end else begin
-                                                               soc_litedramcore_bankmachine1_req_rdata_valid <= soc_litedramcore_bankmachine1_cmd_ready;
-                                                       end
-                                               end else begin
-                                               end
-                                       end else begin
-                                       end
-                               end
-                       end
                end
        endcase
 // synthesis translate_off
@@ -7160,18 +7151,22 @@ end
 reg dummy_d_160;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_bankmachine1_refresh_gnt <= 1'd0;
+       soc_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd0;
        case (vns_bankmachine1_state)
                1'd1: begin
+                       if ((soc_litedramcore_bankmachine1_twtpcon_ready & soc_litedramcore_bankmachine1_trascon_ready)) begin
+                               soc_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
+                       end
                end
                2'd2: begin
                end
                2'd3: begin
+                       if (soc_litedramcore_bankmachine1_trccon_ready) begin
+                               soc_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
+                       end
                end
                3'd4: begin
-                       if (soc_litedramcore_bankmachine1_twtpcon_ready) begin
-                               soc_litedramcore_bankmachine1_refresh_gnt <= 1'd1;
-                       end
+                       soc_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
                end
                3'd5: begin
                end
@@ -7193,19 +7188,13 @@ end
 reg dummy_d_161;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_bankmachine1_cmd_valid <= 1'd0;
+       soc_litedramcore_bankmachine1_cmd_payload_is_read <= 1'd0;
        case (vns_bankmachine1_state)
                1'd1: begin
-                       if ((soc_litedramcore_bankmachine1_twtpcon_ready & soc_litedramcore_bankmachine1_trascon_ready)) begin
-                               soc_litedramcore_bankmachine1_cmd_valid <= 1'd1;
-                       end
                end
                2'd2: begin
                end
                2'd3: begin
-                       if (soc_litedramcore_bankmachine1_trccon_ready) begin
-                               soc_litedramcore_bankmachine1_cmd_valid <= 1'd1;
-                       end
                end
                3'd4: begin
                end
@@ -7223,7 +7212,10 @@ always @(*) begin
                                if (soc_litedramcore_bankmachine1_cmd_buffer_source_valid) begin
                                        if (soc_litedramcore_bankmachine1_row_opened) begin
                                                if (soc_litedramcore_bankmachine1_row_hit) begin
-                                                       soc_litedramcore_bankmachine1_cmd_valid <= 1'd1;
+                                                       if (soc_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
+                                                       end else begin
+                                                               soc_litedramcore_bankmachine1_cmd_payload_is_read <= 1'd1;
+                                                       end
                                                end else begin
                                                end
                                        end else begin
@@ -7241,16 +7233,13 @@ end
 reg dummy_d_162;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_bankmachine1_row_open <= 1'd0;
+       soc_litedramcore_bankmachine1_cmd_payload_is_write <= 1'd0;
        case (vns_bankmachine1_state)
                1'd1: begin
                end
                2'd2: begin
                end
                2'd3: begin
-                       if (soc_litedramcore_bankmachine1_trccon_ready) begin
-                               soc_litedramcore_bankmachine1_row_open <= 1'd1;
-                       end
                end
                3'd4: begin
                end
@@ -7263,6 +7252,21 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
+                       if (soc_litedramcore_bankmachine1_refresh_req) begin
+                       end else begin
+                               if (soc_litedramcore_bankmachine1_cmd_buffer_source_valid) begin
+                                       if (soc_litedramcore_bankmachine1_row_opened) begin
+                                               if (soc_litedramcore_bankmachine1_row_hit) begin
+                                                       if (soc_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
+                                                               soc_litedramcore_bankmachine1_cmd_payload_is_write <= 1'd1;
+                                                       end else begin
+                                                       end
+                                               end else begin
+                                               end
+                                       end else begin
+                                       end
+                               end
+                       end
                end
        endcase
 // synthesis translate_off
@@ -7274,18 +7278,15 @@ end
 reg dummy_d_163;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_bankmachine1_row_close <= 1'd0;
+       soc_litedramcore_bankmachine1_req_wdata_ready <= 1'd0;
        case (vns_bankmachine1_state)
                1'd1: begin
-                       soc_litedramcore_bankmachine1_row_close <= 1'd1;
                end
                2'd2: begin
-                       soc_litedramcore_bankmachine1_row_close <= 1'd1;
                end
                2'd3: begin
                end
                3'd4: begin
-                       soc_litedramcore_bankmachine1_row_close <= 1'd1;
                end
                3'd5: begin
                end
@@ -7296,6 +7297,21 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
+                       if (soc_litedramcore_bankmachine1_refresh_req) begin
+                       end else begin
+                               if (soc_litedramcore_bankmachine1_cmd_buffer_source_valid) begin
+                                       if (soc_litedramcore_bankmachine1_row_opened) begin
+                                               if (soc_litedramcore_bankmachine1_row_hit) begin
+                                                       if (soc_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
+                                                               soc_litedramcore_bankmachine1_req_wdata_ready <= soc_litedramcore_bankmachine1_cmd_ready;
+                                                       end else begin
+                                                       end
+                                               end else begin
+                                               end
+                                       end else begin
+                                       end
+                               end
+                       end
                end
        endcase
 // synthesis translate_off
@@ -7307,7 +7323,7 @@ end
 reg dummy_d_164;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_bankmachine1_cmd_payload_cas <= 1'd0;
+       soc_litedramcore_bankmachine1_req_rdata_valid <= 1'd0;
        case (vns_bankmachine1_state)
                1'd1: begin
                end
@@ -7331,7 +7347,10 @@ always @(*) begin
                                if (soc_litedramcore_bankmachine1_cmd_buffer_source_valid) begin
                                        if (soc_litedramcore_bankmachine1_row_opened) begin
                                                if (soc_litedramcore_bankmachine1_row_hit) begin
-                                                       soc_litedramcore_bankmachine1_cmd_payload_cas <= 1'd1;
+                                                       if (soc_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
+                                                       end else begin
+                                                               soc_litedramcore_bankmachine1_req_rdata_valid <= soc_litedramcore_bankmachine1_cmd_ready;
+                                                       end
                                                end else begin
                                                end
                                        end else begin
@@ -7349,21 +7368,18 @@ end
 reg dummy_d_165;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_bankmachine1_cmd_payload_ras <= 1'd0;
+       soc_litedramcore_bankmachine1_refresh_gnt <= 1'd0;
        case (vns_bankmachine1_state)
                1'd1: begin
-                       if ((soc_litedramcore_bankmachine1_twtpcon_ready & soc_litedramcore_bankmachine1_trascon_ready)) begin
-                               soc_litedramcore_bankmachine1_cmd_payload_ras <= 1'd1;
-                       end
                end
                2'd2: begin
                end
                2'd3: begin
-                       if (soc_litedramcore_bankmachine1_trccon_ready) begin
-                               soc_litedramcore_bankmachine1_cmd_payload_ras <= 1'd1;
-                       end
                end
                3'd4: begin
+                       if (soc_litedramcore_bankmachine1_twtpcon_ready) begin
+                               soc_litedramcore_bankmachine1_refresh_gnt <= 1'd1;
+                       end
                end
                3'd5: begin
                end
@@ -7385,16 +7401,19 @@ end
 reg dummy_d_166;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_bankmachine1_cmd_payload_we <= 1'd0;
+       soc_litedramcore_bankmachine1_cmd_valid <= 1'd0;
        case (vns_bankmachine1_state)
                1'd1: begin
                        if ((soc_litedramcore_bankmachine1_twtpcon_ready & soc_litedramcore_bankmachine1_trascon_ready)) begin
-                               soc_litedramcore_bankmachine1_cmd_payload_we <= 1'd1;
+                               soc_litedramcore_bankmachine1_cmd_valid <= 1'd1;
                        end
                end
                2'd2: begin
                end
                2'd3: begin
+                       if (soc_litedramcore_bankmachine1_trccon_ready) begin
+                               soc_litedramcore_bankmachine1_cmd_valid <= 1'd1;
+                       end
                end
                3'd4: begin
                end
@@ -7412,10 +7431,7 @@ always @(*) begin
                                if (soc_litedramcore_bankmachine1_cmd_buffer_source_valid) begin
                                        if (soc_litedramcore_bankmachine1_row_opened) begin
                                                if (soc_litedramcore_bankmachine1_row_hit) begin
-                                                       if (soc_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
-                                                               soc_litedramcore_bankmachine1_cmd_payload_we <= 1'd1;
-                                                       end else begin
-                                                       end
+                                                       soc_litedramcore_bankmachine1_cmd_valid <= 1'd1;
                                                end else begin
                                                end
                                        end else begin
@@ -7433,22 +7449,18 @@ end
 reg dummy_d_167;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd0;
+       soc_litedramcore_bankmachine1_row_open <= 1'd0;
        case (vns_bankmachine1_state)
                1'd1: begin
-                       if ((soc_litedramcore_bankmachine1_twtpcon_ready & soc_litedramcore_bankmachine1_trascon_ready)) begin
-                               soc_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
-                       end
                end
                2'd2: begin
                end
                2'd3: begin
                        if (soc_litedramcore_bankmachine1_trccon_ready) begin
-                               soc_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
+                               soc_litedramcore_bankmachine1_row_open <= 1'd1;
                        end
                end
                3'd4: begin
-                       soc_litedramcore_bankmachine1_cmd_payload_is_cmd <= 1'd1;
                end
                3'd5: begin
                end
@@ -7470,15 +7482,18 @@ end
 reg dummy_d_168;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_bankmachine1_cmd_payload_is_read <= 1'd0;
+       soc_litedramcore_bankmachine1_row_close <= 1'd0;
        case (vns_bankmachine1_state)
                1'd1: begin
+                       soc_litedramcore_bankmachine1_row_close <= 1'd1;
                end
                2'd2: begin
+                       soc_litedramcore_bankmachine1_row_close <= 1'd1;
                end
                2'd3: begin
                end
                3'd4: begin
+                       soc_litedramcore_bankmachine1_row_close <= 1'd1;
                end
                3'd5: begin
                end
@@ -7489,21 +7504,6 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
-                       if (soc_litedramcore_bankmachine1_refresh_req) begin
-                       end else begin
-                               if (soc_litedramcore_bankmachine1_cmd_buffer_source_valid) begin
-                                       if (soc_litedramcore_bankmachine1_row_opened) begin
-                                               if (soc_litedramcore_bankmachine1_row_hit) begin
-                                                       if (soc_litedramcore_bankmachine1_cmd_buffer_source_payload_we) begin
-                                                       end else begin
-                                                               soc_litedramcore_bankmachine1_cmd_payload_is_read <= 1'd1;
-                                                       end
-                                               end else begin
-                                               end
-                                       end else begin
-                                       end
-                               end
-                       end
                end
        endcase
 // synthesis translate_off
@@ -7670,7 +7670,7 @@ end
 reg dummy_d_173;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_bankmachine2_cmd_payload_is_write <= 1'd0;
+       soc_litedramcore_bankmachine2_cmd_payload_cas <= 1'd0;
        case (vns_bankmachine2_state)
                1'd1: begin
                end
@@ -7694,10 +7694,7 @@ always @(*) begin
                                if (soc_litedramcore_bankmachine2_cmd_buffer_source_valid) begin
                                        if (soc_litedramcore_bankmachine2_row_opened) begin
                                                if (soc_litedramcore_bankmachine2_row_hit) begin
-                                                       if (soc_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
-                                                               soc_litedramcore_bankmachine2_cmd_payload_is_write <= 1'd1;
-                                                       end else begin
-                                                       end
+                                                       soc_litedramcore_bankmachine2_cmd_payload_cas <= 1'd1;
                                                end else begin
                                                end
                                        end else begin
@@ -7715,13 +7712,19 @@ end
 reg dummy_d_174;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_bankmachine2_req_wdata_ready <= 1'd0;
+       soc_litedramcore_bankmachine2_cmd_payload_ras <= 1'd0;
        case (vns_bankmachine2_state)
                1'd1: begin
+                       if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin
+                               soc_litedramcore_bankmachine2_cmd_payload_ras <= 1'd1;
+                       end
                end
                2'd2: begin
                end
                2'd3: begin
+                       if (soc_litedramcore_bankmachine2_trccon_ready) begin
+                               soc_litedramcore_bankmachine2_cmd_payload_ras <= 1'd1;
+                       end
                end
                3'd4: begin
                end
@@ -7734,21 +7737,6 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
-                       if (soc_litedramcore_bankmachine2_refresh_req) begin
-                       end else begin
-                               if (soc_litedramcore_bankmachine2_cmd_buffer_source_valid) begin
-                                       if (soc_litedramcore_bankmachine2_row_opened) begin
-                                               if (soc_litedramcore_bankmachine2_row_hit) begin
-                                                       if (soc_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
-                                                               soc_litedramcore_bankmachine2_req_wdata_ready <= soc_litedramcore_bankmachine2_cmd_ready;
-                                                       end else begin
-                                                       end
-                                               end else begin
-                                               end
-                                       end else begin
-                                       end
-                               end
-                       end
                end
        endcase
 // synthesis translate_off
@@ -7760,9 +7748,12 @@ end
 reg dummy_d_175;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_bankmachine2_req_rdata_valid <= 1'd0;
+       soc_litedramcore_bankmachine2_cmd_payload_we <= 1'd0;
        case (vns_bankmachine2_state)
                1'd1: begin
+                       if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin
+                               soc_litedramcore_bankmachine2_cmd_payload_we <= 1'd1;
+                       end
                end
                2'd2: begin
                end
@@ -7785,8 +7776,8 @@ always @(*) begin
                                        if (soc_litedramcore_bankmachine2_row_opened) begin
                                                if (soc_litedramcore_bankmachine2_row_hit) begin
                                                        if (soc_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
+                                                               soc_litedramcore_bankmachine2_cmd_payload_we <= 1'd1;
                                                        end else begin
-                                                               soc_litedramcore_bankmachine2_req_rdata_valid <= soc_litedramcore_bankmachine2_cmd_ready;
                                                        end
                                                end else begin
                                                end
@@ -7805,18 +7796,18 @@ end
 reg dummy_d_176;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_bankmachine2_refresh_gnt <= 1'd0;
+       soc_litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0;
        case (vns_bankmachine2_state)
                1'd1: begin
                end
                2'd2: begin
                end
                2'd3: begin
+                       if (soc_litedramcore_bankmachine2_trccon_ready) begin
+                               soc_litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd1;
+                       end
                end
                3'd4: begin
-                       if (soc_litedramcore_bankmachine2_twtpcon_ready) begin
-                               soc_litedramcore_bankmachine2_refresh_gnt <= 1'd1;
-                       end
                end
                3'd5: begin
                end
@@ -7838,21 +7829,22 @@ end
 reg dummy_d_177;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_bankmachine2_cmd_valid <= 1'd0;
+       soc_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd0;
        case (vns_bankmachine2_state)
                1'd1: begin
                        if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin
-                               soc_litedramcore_bankmachine2_cmd_valid <= 1'd1;
+                               soc_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
                        end
                end
                2'd2: begin
                end
                2'd3: begin
                        if (soc_litedramcore_bankmachine2_trccon_ready) begin
-                               soc_litedramcore_bankmachine2_cmd_valid <= 1'd1;
+                               soc_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
                        end
                end
                3'd4: begin
+                       soc_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
                end
                3'd5: begin
                end
@@ -7863,18 +7855,6 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
-                       if (soc_litedramcore_bankmachine2_refresh_req) begin
-                       end else begin
-                               if (soc_litedramcore_bankmachine2_cmd_buffer_source_valid) begin
-                                       if (soc_litedramcore_bankmachine2_row_opened) begin
-                                               if (soc_litedramcore_bankmachine2_row_hit) begin
-                                                       soc_litedramcore_bankmachine2_cmd_valid <= 1'd1;
-                                               end else begin
-                                               end
-                                       end else begin
-                                       end
-                               end
-                       end
                end
        endcase
 // synthesis translate_off
@@ -7886,16 +7866,13 @@ end
 reg dummy_d_178;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd0;
+       soc_litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0;
        case (vns_bankmachine2_state)
                1'd1: begin
                end
                2'd2: begin
                end
                2'd3: begin
-                       if (soc_litedramcore_bankmachine2_trccon_ready) begin
-                               soc_litedramcore_bankmachine2_row_col_n_addr_sel <= 1'd1;
-                       end
                end
                3'd4: begin
                end
@@ -7908,6 +7885,21 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
+                       if (soc_litedramcore_bankmachine2_refresh_req) begin
+                       end else begin
+                               if (soc_litedramcore_bankmachine2_cmd_buffer_source_valid) begin
+                                       if (soc_litedramcore_bankmachine2_row_opened) begin
+                                               if (soc_litedramcore_bankmachine2_row_hit) begin
+                                                       if (soc_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
+                                                       end else begin
+                                                               soc_litedramcore_bankmachine2_cmd_payload_is_read <= 1'd1;
+                                                       end
+                                               end else begin
+                                               end
+                                       end else begin
+                                       end
+                               end
+                       end
                end
        endcase
 // synthesis translate_off
@@ -7919,16 +7911,13 @@ end
 reg dummy_d_179;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_bankmachine2_row_open <= 1'd0;
+       soc_litedramcore_bankmachine2_cmd_payload_is_write <= 1'd0;
        case (vns_bankmachine2_state)
                1'd1: begin
                end
                2'd2: begin
                end
                2'd3: begin
-                       if (soc_litedramcore_bankmachine2_trccon_ready) begin
-                               soc_litedramcore_bankmachine2_row_open <= 1'd1;
-                       end
                end
                3'd4: begin
                end
@@ -7941,6 +7930,21 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
+                       if (soc_litedramcore_bankmachine2_refresh_req) begin
+                       end else begin
+                               if (soc_litedramcore_bankmachine2_cmd_buffer_source_valid) begin
+                                       if (soc_litedramcore_bankmachine2_row_opened) begin
+                                               if (soc_litedramcore_bankmachine2_row_hit) begin
+                                                       if (soc_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
+                                                               soc_litedramcore_bankmachine2_cmd_payload_is_write <= 1'd1;
+                                                       end else begin
+                                                       end
+                                               end else begin
+                                               end
+                                       end else begin
+                                       end
+                               end
+                       end
                end
        endcase
 // synthesis translate_off
@@ -7952,18 +7956,15 @@ end
 reg dummy_d_180;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_bankmachine2_row_close <= 1'd0;
+       soc_litedramcore_bankmachine2_req_wdata_ready <= 1'd0;
        case (vns_bankmachine2_state)
                1'd1: begin
-                       soc_litedramcore_bankmachine2_row_close <= 1'd1;
                end
                2'd2: begin
-                       soc_litedramcore_bankmachine2_row_close <= 1'd1;
                end
                2'd3: begin
                end
                3'd4: begin
-                       soc_litedramcore_bankmachine2_row_close <= 1'd1;
                end
                3'd5: begin
                end
@@ -7974,6 +7975,21 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
+                       if (soc_litedramcore_bankmachine2_refresh_req) begin
+                       end else begin
+                               if (soc_litedramcore_bankmachine2_cmd_buffer_source_valid) begin
+                                       if (soc_litedramcore_bankmachine2_row_opened) begin
+                                               if (soc_litedramcore_bankmachine2_row_hit) begin
+                                                       if (soc_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
+                                                               soc_litedramcore_bankmachine2_req_wdata_ready <= soc_litedramcore_bankmachine2_cmd_ready;
+                                                       end else begin
+                                                       end
+                                               end else begin
+                                               end
+                                       end else begin
+                                       end
+                               end
+                       end
                end
        endcase
 // synthesis translate_off
@@ -7985,7 +8001,7 @@ end
 reg dummy_d_181;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_bankmachine2_cmd_payload_cas <= 1'd0;
+       soc_litedramcore_bankmachine2_req_rdata_valid <= 1'd0;
        case (vns_bankmachine2_state)
                1'd1: begin
                end
@@ -8009,7 +8025,10 @@ always @(*) begin
                                if (soc_litedramcore_bankmachine2_cmd_buffer_source_valid) begin
                                        if (soc_litedramcore_bankmachine2_row_opened) begin
                                                if (soc_litedramcore_bankmachine2_row_hit) begin
-                                                       soc_litedramcore_bankmachine2_cmd_payload_cas <= 1'd1;
+                                                       if (soc_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
+                                                       end else begin
+                                                               soc_litedramcore_bankmachine2_req_rdata_valid <= soc_litedramcore_bankmachine2_cmd_ready;
+                                                       end
                                                end else begin
                                                end
                                        end else begin
@@ -8027,21 +8046,18 @@ end
 reg dummy_d_182;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_bankmachine2_cmd_payload_ras <= 1'd0;
+       soc_litedramcore_bankmachine2_refresh_gnt <= 1'd0;
        case (vns_bankmachine2_state)
                1'd1: begin
-                       if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin
-                               soc_litedramcore_bankmachine2_cmd_payload_ras <= 1'd1;
-                       end
                end
                2'd2: begin
                end
                2'd3: begin
-                       if (soc_litedramcore_bankmachine2_trccon_ready) begin
-                               soc_litedramcore_bankmachine2_cmd_payload_ras <= 1'd1;
-                       end
                end
                3'd4: begin
+                       if (soc_litedramcore_bankmachine2_twtpcon_ready) begin
+                               soc_litedramcore_bankmachine2_refresh_gnt <= 1'd1;
+                       end
                end
                3'd5: begin
                end
@@ -8063,16 +8079,19 @@ end
 reg dummy_d_183;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_bankmachine2_cmd_payload_we <= 1'd0;
+       soc_litedramcore_bankmachine2_cmd_valid <= 1'd0;
        case (vns_bankmachine2_state)
                1'd1: begin
                        if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin
-                               soc_litedramcore_bankmachine2_cmd_payload_we <= 1'd1;
+                               soc_litedramcore_bankmachine2_cmd_valid <= 1'd1;
                        end
                end
                2'd2: begin
                end
                2'd3: begin
+                       if (soc_litedramcore_bankmachine2_trccon_ready) begin
+                               soc_litedramcore_bankmachine2_cmd_valid <= 1'd1;
+                       end
                end
                3'd4: begin
                end
@@ -8090,10 +8109,7 @@ always @(*) begin
                                if (soc_litedramcore_bankmachine2_cmd_buffer_source_valid) begin
                                        if (soc_litedramcore_bankmachine2_row_opened) begin
                                                if (soc_litedramcore_bankmachine2_row_hit) begin
-                                                       if (soc_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
-                                                               soc_litedramcore_bankmachine2_cmd_payload_we <= 1'd1;
-                                                       end else begin
-                                                       end
+                                                       soc_litedramcore_bankmachine2_cmd_valid <= 1'd1;
                                                end else begin
                                                end
                                        end else begin
@@ -8111,22 +8127,18 @@ end
 reg dummy_d_184;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd0;
+       soc_litedramcore_bankmachine2_row_open <= 1'd0;
        case (vns_bankmachine2_state)
                1'd1: begin
-                       if ((soc_litedramcore_bankmachine2_twtpcon_ready & soc_litedramcore_bankmachine2_trascon_ready)) begin
-                               soc_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
-                       end
                end
                2'd2: begin
                end
                2'd3: begin
                        if (soc_litedramcore_bankmachine2_trccon_ready) begin
-                               soc_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
+                               soc_litedramcore_bankmachine2_row_open <= 1'd1;
                        end
                end
                3'd4: begin
-                       soc_litedramcore_bankmachine2_cmd_payload_is_cmd <= 1'd1;
                end
                3'd5: begin
                end
@@ -8148,15 +8160,18 @@ end
 reg dummy_d_185;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_bankmachine2_cmd_payload_is_read <= 1'd0;
+       soc_litedramcore_bankmachine2_row_close <= 1'd0;
        case (vns_bankmachine2_state)
                1'd1: begin
+                       soc_litedramcore_bankmachine2_row_close <= 1'd1;
                end
                2'd2: begin
+                       soc_litedramcore_bankmachine2_row_close <= 1'd1;
                end
                2'd3: begin
                end
                3'd4: begin
+                       soc_litedramcore_bankmachine2_row_close <= 1'd1;
                end
                3'd5: begin
                end
@@ -8167,21 +8182,6 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
-                       if (soc_litedramcore_bankmachine2_refresh_req) begin
-                       end else begin
-                               if (soc_litedramcore_bankmachine2_cmd_buffer_source_valid) begin
-                                       if (soc_litedramcore_bankmachine2_row_opened) begin
-                                               if (soc_litedramcore_bankmachine2_row_hit) begin
-                                                       if (soc_litedramcore_bankmachine2_cmd_buffer_source_payload_we) begin
-                                                       end else begin
-                                                               soc_litedramcore_bankmachine2_cmd_payload_is_read <= 1'd1;
-                                                       end
-                                               end else begin
-                                               end
-                                       end else begin
-                                       end
-                               end
-                       end
                end
        endcase
 // synthesis translate_off
@@ -8348,7 +8348,7 @@ end
 reg dummy_d_190;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_bankmachine3_cmd_payload_is_write <= 1'd0;
+       soc_litedramcore_bankmachine3_cmd_payload_cas <= 1'd0;
        case (vns_bankmachine3_state)
                1'd1: begin
                end
@@ -8372,10 +8372,7 @@ always @(*) begin
                                if (soc_litedramcore_bankmachine3_cmd_buffer_source_valid) begin
                                        if (soc_litedramcore_bankmachine3_row_opened) begin
                                                if (soc_litedramcore_bankmachine3_row_hit) begin
-                                                       if (soc_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
-                                                               soc_litedramcore_bankmachine3_cmd_payload_is_write <= 1'd1;
-                                                       end else begin
-                                                       end
+                                                       soc_litedramcore_bankmachine3_cmd_payload_cas <= 1'd1;
                                                end else begin
                                                end
                                        end else begin
@@ -8393,13 +8390,19 @@ end
 reg dummy_d_191;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_bankmachine3_req_wdata_ready <= 1'd0;
+       soc_litedramcore_bankmachine3_cmd_payload_ras <= 1'd0;
        case (vns_bankmachine3_state)
                1'd1: begin
+                       if ((soc_litedramcore_bankmachine3_twtpcon_ready & soc_litedramcore_bankmachine3_trascon_ready)) begin
+                               soc_litedramcore_bankmachine3_cmd_payload_ras <= 1'd1;
+                       end
                end
                2'd2: begin
                end
                2'd3: begin
+                       if (soc_litedramcore_bankmachine3_trccon_ready) begin
+                               soc_litedramcore_bankmachine3_cmd_payload_ras <= 1'd1;
+                       end
                end
                3'd4: begin
                end
@@ -8412,21 +8415,6 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
-                       if (soc_litedramcore_bankmachine3_refresh_req) begin
-                       end else begin
-                               if (soc_litedramcore_bankmachine3_cmd_buffer_source_valid) begin
-                                       if (soc_litedramcore_bankmachine3_row_opened) begin
-                                               if (soc_litedramcore_bankmachine3_row_hit) begin
-                                                       if (soc_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
-                                                               soc_litedramcore_bankmachine3_req_wdata_ready <= soc_litedramcore_bankmachine3_cmd_ready;
-                                                       end else begin
-                                                       end
-                                               end else begin
-                                               end
-                                       end else begin
-                                       end
-                               end
-                       end
                end
        endcase
 // synthesis translate_off
@@ -8438,9 +8426,12 @@ end
 reg dummy_d_192;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_bankmachine3_req_rdata_valid <= 1'd0;
+       soc_litedramcore_bankmachine3_cmd_payload_we <= 1'd0;
        case (vns_bankmachine3_state)
                1'd1: begin
+                       if ((soc_litedramcore_bankmachine3_twtpcon_ready & soc_litedramcore_bankmachine3_trascon_ready)) begin
+                               soc_litedramcore_bankmachine3_cmd_payload_we <= 1'd1;
+                       end
                end
                2'd2: begin
                end
@@ -8463,8 +8454,8 @@ always @(*) begin
                                        if (soc_litedramcore_bankmachine3_row_opened) begin
                                                if (soc_litedramcore_bankmachine3_row_hit) begin
                                                        if (soc_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
+                                                               soc_litedramcore_bankmachine3_cmd_payload_we <= 1'd1;
                                                        end else begin
-                                                               soc_litedramcore_bankmachine3_req_rdata_valid <= soc_litedramcore_bankmachine3_cmd_ready;
                                                        end
                                                end else begin
                                                end
@@ -8483,18 +8474,18 @@ end
 reg dummy_d_193;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_bankmachine3_refresh_gnt <= 1'd0;
+       soc_litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0;
        case (vns_bankmachine3_state)
                1'd1: begin
                end
                2'd2: begin
                end
                2'd3: begin
+                       if (soc_litedramcore_bankmachine3_trccon_ready) begin
+                               soc_litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd1;
+                       end
                end
                3'd4: begin
-                       if (soc_litedramcore_bankmachine3_twtpcon_ready) begin
-                               soc_litedramcore_bankmachine3_refresh_gnt <= 1'd1;
-                       end
                end
                3'd5: begin
                end
@@ -8516,21 +8507,22 @@ end
 reg dummy_d_194;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_bankmachine3_cmd_valid <= 1'd0;
+       soc_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd0;
        case (vns_bankmachine3_state)
                1'd1: begin
                        if ((soc_litedramcore_bankmachine3_twtpcon_ready & soc_litedramcore_bankmachine3_trascon_ready)) begin
-                               soc_litedramcore_bankmachine3_cmd_valid <= 1'd1;
+                               soc_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
                        end
                end
                2'd2: begin
                end
                2'd3: begin
                        if (soc_litedramcore_bankmachine3_trccon_ready) begin
-                               soc_litedramcore_bankmachine3_cmd_valid <= 1'd1;
+                               soc_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
                        end
                end
                3'd4: begin
+                       soc_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
                end
                3'd5: begin
                end
@@ -8541,18 +8533,6 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
-                       if (soc_litedramcore_bankmachine3_refresh_req) begin
-                       end else begin
-                               if (soc_litedramcore_bankmachine3_cmd_buffer_source_valid) begin
-                                       if (soc_litedramcore_bankmachine3_row_opened) begin
-                                               if (soc_litedramcore_bankmachine3_row_hit) begin
-                                                       soc_litedramcore_bankmachine3_cmd_valid <= 1'd1;
-                                               end else begin
-                                               end
-                                       end else begin
-                                       end
-                               end
-                       end
                end
        endcase
 // synthesis translate_off
@@ -8564,16 +8544,13 @@ end
 reg dummy_d_195;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_bankmachine3_row_open <= 1'd0;
+       soc_litedramcore_bankmachine3_cmd_payload_is_read <= 1'd0;
        case (vns_bankmachine3_state)
                1'd1: begin
                end
                2'd2: begin
                end
                2'd3: begin
-                       if (soc_litedramcore_bankmachine3_trccon_ready) begin
-                               soc_litedramcore_bankmachine3_row_open <= 1'd1;
-                       end
                end
                3'd4: begin
                end
@@ -8586,6 +8563,21 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
+                       if (soc_litedramcore_bankmachine3_refresh_req) begin
+                       end else begin
+                               if (soc_litedramcore_bankmachine3_cmd_buffer_source_valid) begin
+                                       if (soc_litedramcore_bankmachine3_row_opened) begin
+                                               if (soc_litedramcore_bankmachine3_row_hit) begin
+                                                       if (soc_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
+                                                       end else begin
+                                                               soc_litedramcore_bankmachine3_cmd_payload_is_read <= 1'd1;
+                                                       end
+                                               end else begin
+                                               end
+                                       end else begin
+                                       end
+                               end
+                       end
                end
        endcase
 // synthesis translate_off
@@ -8597,18 +8589,15 @@ end
 reg dummy_d_196;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_bankmachine3_row_close <= 1'd0;
+       soc_litedramcore_bankmachine3_cmd_payload_is_write <= 1'd0;
        case (vns_bankmachine3_state)
                1'd1: begin
-                       soc_litedramcore_bankmachine3_row_close <= 1'd1;
                end
                2'd2: begin
-                       soc_litedramcore_bankmachine3_row_close <= 1'd1;
                end
                2'd3: begin
                end
                3'd4: begin
-                       soc_litedramcore_bankmachine3_row_close <= 1'd1;
                end
                3'd5: begin
                end
@@ -8619,6 +8608,21 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
+                       if (soc_litedramcore_bankmachine3_refresh_req) begin
+                       end else begin
+                               if (soc_litedramcore_bankmachine3_cmd_buffer_source_valid) begin
+                                       if (soc_litedramcore_bankmachine3_row_opened) begin
+                                               if (soc_litedramcore_bankmachine3_row_hit) begin
+                                                       if (soc_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
+                                                               soc_litedramcore_bankmachine3_cmd_payload_is_write <= 1'd1;
+                                                       end else begin
+                                                       end
+                                               end else begin
+                                               end
+                                       end else begin
+                                       end
+                               end
+                       end
                end
        endcase
 // synthesis translate_off
@@ -8630,16 +8634,13 @@ end
 reg dummy_d_197;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd0;
+       soc_litedramcore_bankmachine3_req_wdata_ready <= 1'd0;
        case (vns_bankmachine3_state)
                1'd1: begin
                end
                2'd2: begin
                end
                2'd3: begin
-                       if (soc_litedramcore_bankmachine3_trccon_ready) begin
-                               soc_litedramcore_bankmachine3_row_col_n_addr_sel <= 1'd1;
-                       end
                end
                3'd4: begin
                end
@@ -8652,6 +8653,21 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
+                       if (soc_litedramcore_bankmachine3_refresh_req) begin
+                       end else begin
+                               if (soc_litedramcore_bankmachine3_cmd_buffer_source_valid) begin
+                                       if (soc_litedramcore_bankmachine3_row_opened) begin
+                                               if (soc_litedramcore_bankmachine3_row_hit) begin
+                                                       if (soc_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
+                                                               soc_litedramcore_bankmachine3_req_wdata_ready <= soc_litedramcore_bankmachine3_cmd_ready;
+                                                       end else begin
+                                                       end
+                                               end else begin
+                                               end
+                                       end else begin
+                                       end
+                               end
+                       end
                end
        endcase
 // synthesis translate_off
@@ -8663,7 +8679,7 @@ end
 reg dummy_d_198;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_bankmachine3_cmd_payload_cas <= 1'd0;
+       soc_litedramcore_bankmachine3_req_rdata_valid <= 1'd0;
        case (vns_bankmachine3_state)
                1'd1: begin
                end
@@ -8687,7 +8703,10 @@ always @(*) begin
                                if (soc_litedramcore_bankmachine3_cmd_buffer_source_valid) begin
                                        if (soc_litedramcore_bankmachine3_row_opened) begin
                                                if (soc_litedramcore_bankmachine3_row_hit) begin
-                                                       soc_litedramcore_bankmachine3_cmd_payload_cas <= 1'd1;
+                                                       if (soc_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
+                                                       end else begin
+                                                               soc_litedramcore_bankmachine3_req_rdata_valid <= soc_litedramcore_bankmachine3_cmd_ready;
+                                                       end
                                                end else begin
                                                end
                                        end else begin
@@ -8705,21 +8724,18 @@ end
 reg dummy_d_199;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_bankmachine3_cmd_payload_ras <= 1'd0;
+       soc_litedramcore_bankmachine3_refresh_gnt <= 1'd0;
        case (vns_bankmachine3_state)
                1'd1: begin
-                       if ((soc_litedramcore_bankmachine3_twtpcon_ready & soc_litedramcore_bankmachine3_trascon_ready)) begin
-                               soc_litedramcore_bankmachine3_cmd_payload_ras <= 1'd1;
-                       end
                end
                2'd2: begin
                end
                2'd3: begin
-                       if (soc_litedramcore_bankmachine3_trccon_ready) begin
-                               soc_litedramcore_bankmachine3_cmd_payload_ras <= 1'd1;
-                       end
                end
                3'd4: begin
+                       if (soc_litedramcore_bankmachine3_twtpcon_ready) begin
+                               soc_litedramcore_bankmachine3_refresh_gnt <= 1'd1;
+                       end
                end
                3'd5: begin
                end
@@ -8741,16 +8757,19 @@ end
 reg dummy_d_200;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_bankmachine3_cmd_payload_we <= 1'd0;
+       soc_litedramcore_bankmachine3_cmd_valid <= 1'd0;
        case (vns_bankmachine3_state)
                1'd1: begin
                        if ((soc_litedramcore_bankmachine3_twtpcon_ready & soc_litedramcore_bankmachine3_trascon_ready)) begin
-                               soc_litedramcore_bankmachine3_cmd_payload_we <= 1'd1;
+                               soc_litedramcore_bankmachine3_cmd_valid <= 1'd1;
                        end
                end
                2'd2: begin
                end
                2'd3: begin
+                       if (soc_litedramcore_bankmachine3_trccon_ready) begin
+                               soc_litedramcore_bankmachine3_cmd_valid <= 1'd1;
+                       end
                end
                3'd4: begin
                end
@@ -8768,10 +8787,7 @@ always @(*) begin
                                if (soc_litedramcore_bankmachine3_cmd_buffer_source_valid) begin
                                        if (soc_litedramcore_bankmachine3_row_opened) begin
                                                if (soc_litedramcore_bankmachine3_row_hit) begin
-                                                       if (soc_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
-                                                               soc_litedramcore_bankmachine3_cmd_payload_we <= 1'd1;
-                                                       end else begin
-                                                       end
+                                                       soc_litedramcore_bankmachine3_cmd_valid <= 1'd1;
                                                end else begin
                                                end
                                        end else begin
@@ -8789,22 +8805,18 @@ end
 reg dummy_d_201;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd0;
+       soc_litedramcore_bankmachine3_row_open <= 1'd0;
        case (vns_bankmachine3_state)
                1'd1: begin
-                       if ((soc_litedramcore_bankmachine3_twtpcon_ready & soc_litedramcore_bankmachine3_trascon_ready)) begin
-                               soc_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
-                       end
                end
                2'd2: begin
                end
                2'd3: begin
                        if (soc_litedramcore_bankmachine3_trccon_ready) begin
-                               soc_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
+                               soc_litedramcore_bankmachine3_row_open <= 1'd1;
                        end
                end
                3'd4: begin
-                       soc_litedramcore_bankmachine3_cmd_payload_is_cmd <= 1'd1;
                end
                3'd5: begin
                end
@@ -8826,15 +8838,18 @@ end
 reg dummy_d_202;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_bankmachine3_cmd_payload_is_read <= 1'd0;
+       soc_litedramcore_bankmachine3_row_close <= 1'd0;
        case (vns_bankmachine3_state)
                1'd1: begin
+                       soc_litedramcore_bankmachine3_row_close <= 1'd1;
                end
                2'd2: begin
+                       soc_litedramcore_bankmachine3_row_close <= 1'd1;
                end
                2'd3: begin
                end
                3'd4: begin
+                       soc_litedramcore_bankmachine3_row_close <= 1'd1;
                end
                3'd5: begin
                end
@@ -8845,21 +8860,6 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
-                       if (soc_litedramcore_bankmachine3_refresh_req) begin
-                       end else begin
-                               if (soc_litedramcore_bankmachine3_cmd_buffer_source_valid) begin
-                                       if (soc_litedramcore_bankmachine3_row_opened) begin
-                                               if (soc_litedramcore_bankmachine3_row_hit) begin
-                                                       if (soc_litedramcore_bankmachine3_cmd_buffer_source_payload_we) begin
-                                                       end else begin
-                                                               soc_litedramcore_bankmachine3_cmd_payload_is_read <= 1'd1;
-                                                       end
-                                               end else begin
-                                               end
-                                       end else begin
-                                       end
-                               end
-                       end
                end
        endcase
 // synthesis translate_off
@@ -9026,7 +9026,7 @@ end
 reg dummy_d_207;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_bankmachine4_cmd_payload_is_write <= 1'd0;
+       soc_litedramcore_bankmachine4_cmd_payload_cas <= 1'd0;
        case (vns_bankmachine4_state)
                1'd1: begin
                end
@@ -9050,10 +9050,7 @@ always @(*) begin
                                if (soc_litedramcore_bankmachine4_cmd_buffer_source_valid) begin
                                        if (soc_litedramcore_bankmachine4_row_opened) begin
                                                if (soc_litedramcore_bankmachine4_row_hit) begin
-                                                       if (soc_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
-                                                               soc_litedramcore_bankmachine4_cmd_payload_is_write <= 1'd1;
-                                                       end else begin
-                                                       end
+                                                       soc_litedramcore_bankmachine4_cmd_payload_cas <= 1'd1;
                                                end else begin
                                                end
                                        end else begin
@@ -9071,13 +9068,19 @@ end
 reg dummy_d_208;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_bankmachine4_req_wdata_ready <= 1'd0;
+       soc_litedramcore_bankmachine4_cmd_payload_ras <= 1'd0;
        case (vns_bankmachine4_state)
                1'd1: begin
+                       if ((soc_litedramcore_bankmachine4_twtpcon_ready & soc_litedramcore_bankmachine4_trascon_ready)) begin
+                               soc_litedramcore_bankmachine4_cmd_payload_ras <= 1'd1;
+                       end
                end
                2'd2: begin
                end
                2'd3: begin
+                       if (soc_litedramcore_bankmachine4_trccon_ready) begin
+                               soc_litedramcore_bankmachine4_cmd_payload_ras <= 1'd1;
+                       end
                end
                3'd4: begin
                end
@@ -9090,21 +9093,6 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
-                       if (soc_litedramcore_bankmachine4_refresh_req) begin
-                       end else begin
-                               if (soc_litedramcore_bankmachine4_cmd_buffer_source_valid) begin
-                                       if (soc_litedramcore_bankmachine4_row_opened) begin
-                                               if (soc_litedramcore_bankmachine4_row_hit) begin
-                                                       if (soc_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
-                                                               soc_litedramcore_bankmachine4_req_wdata_ready <= soc_litedramcore_bankmachine4_cmd_ready;
-                                                       end else begin
-                                                       end
-                                               end else begin
-                                               end
-                                       end else begin
-                                       end
-                               end
-                       end
                end
        endcase
 // synthesis translate_off
@@ -9116,9 +9104,12 @@ end
 reg dummy_d_209;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_bankmachine4_req_rdata_valid <= 1'd0;
+       soc_litedramcore_bankmachine4_cmd_payload_we <= 1'd0;
        case (vns_bankmachine4_state)
                1'd1: begin
+                       if ((soc_litedramcore_bankmachine4_twtpcon_ready & soc_litedramcore_bankmachine4_trascon_ready)) begin
+                               soc_litedramcore_bankmachine4_cmd_payload_we <= 1'd1;
+                       end
                end
                2'd2: begin
                end
@@ -9141,8 +9132,8 @@ always @(*) begin
                                        if (soc_litedramcore_bankmachine4_row_opened) begin
                                                if (soc_litedramcore_bankmachine4_row_hit) begin
                                                        if (soc_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
+                                                               soc_litedramcore_bankmachine4_cmd_payload_we <= 1'd1;
                                                        end else begin
-                                                               soc_litedramcore_bankmachine4_req_rdata_valid <= soc_litedramcore_bankmachine4_cmd_ready;
                                                        end
                                                end else begin
                                                end
@@ -9161,18 +9152,18 @@ end
 reg dummy_d_210;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_bankmachine4_refresh_gnt <= 1'd0;
+       soc_litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0;
        case (vns_bankmachine4_state)
                1'd1: begin
                end
                2'd2: begin
                end
                2'd3: begin
+                       if (soc_litedramcore_bankmachine4_trccon_ready) begin
+                               soc_litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd1;
+                       end
                end
                3'd4: begin
-                       if (soc_litedramcore_bankmachine4_twtpcon_ready) begin
-                               soc_litedramcore_bankmachine4_refresh_gnt <= 1'd1;
-                       end
                end
                3'd5: begin
                end
@@ -9194,21 +9185,22 @@ end
 reg dummy_d_211;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_bankmachine4_cmd_valid <= 1'd0;
+       soc_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0;
        case (vns_bankmachine4_state)
                1'd1: begin
                        if ((soc_litedramcore_bankmachine4_twtpcon_ready & soc_litedramcore_bankmachine4_trascon_ready)) begin
-                               soc_litedramcore_bankmachine4_cmd_valid <= 1'd1;
+                               soc_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
                        end
                end
                2'd2: begin
                end
                2'd3: begin
                        if (soc_litedramcore_bankmachine4_trccon_ready) begin
-                               soc_litedramcore_bankmachine4_cmd_valid <= 1'd1;
+                               soc_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
                        end
                end
                3'd4: begin
+                       soc_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
                end
                3'd5: begin
                end
@@ -9219,18 +9211,6 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
-                       if (soc_litedramcore_bankmachine4_refresh_req) begin
-                       end else begin
-                               if (soc_litedramcore_bankmachine4_cmd_buffer_source_valid) begin
-                                       if (soc_litedramcore_bankmachine4_row_opened) begin
-                                               if (soc_litedramcore_bankmachine4_row_hit) begin
-                                                       soc_litedramcore_bankmachine4_cmd_valid <= 1'd1;
-                                               end else begin
-                                               end
-                                       end else begin
-                                       end
-                               end
-                       end
                end
        endcase
 // synthesis translate_off
@@ -9242,16 +9222,13 @@ end
 reg dummy_d_212;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_bankmachine4_row_open <= 1'd0;
+       soc_litedramcore_bankmachine4_cmd_payload_is_read <= 1'd0;
        case (vns_bankmachine4_state)
                1'd1: begin
                end
                2'd2: begin
                end
                2'd3: begin
-                       if (soc_litedramcore_bankmachine4_trccon_ready) begin
-                               soc_litedramcore_bankmachine4_row_open <= 1'd1;
-                       end
                end
                3'd4: begin
                end
@@ -9264,6 +9241,21 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
+                       if (soc_litedramcore_bankmachine4_refresh_req) begin
+                       end else begin
+                               if (soc_litedramcore_bankmachine4_cmd_buffer_source_valid) begin
+                                       if (soc_litedramcore_bankmachine4_row_opened) begin
+                                               if (soc_litedramcore_bankmachine4_row_hit) begin
+                                                       if (soc_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
+                                                       end else begin
+                                                               soc_litedramcore_bankmachine4_cmd_payload_is_read <= 1'd1;
+                                                       end
+                                               end else begin
+                                               end
+                                       end else begin
+                                       end
+                               end
+                       end
                end
        endcase
 // synthesis translate_off
@@ -9275,18 +9267,15 @@ end
 reg dummy_d_213;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_bankmachine4_row_close <= 1'd0;
+       soc_litedramcore_bankmachine4_cmd_payload_is_write <= 1'd0;
        case (vns_bankmachine4_state)
                1'd1: begin
-                       soc_litedramcore_bankmachine4_row_close <= 1'd1;
                end
                2'd2: begin
-                       soc_litedramcore_bankmachine4_row_close <= 1'd1;
                end
                2'd3: begin
                end
                3'd4: begin
-                       soc_litedramcore_bankmachine4_row_close <= 1'd1;
                end
                3'd5: begin
                end
@@ -9297,6 +9286,21 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
+                       if (soc_litedramcore_bankmachine4_refresh_req) begin
+                       end else begin
+                               if (soc_litedramcore_bankmachine4_cmd_buffer_source_valid) begin
+                                       if (soc_litedramcore_bankmachine4_row_opened) begin
+                                               if (soc_litedramcore_bankmachine4_row_hit) begin
+                                                       if (soc_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
+                                                               soc_litedramcore_bankmachine4_cmd_payload_is_write <= 1'd1;
+                                                       end else begin
+                                                       end
+                                               end else begin
+                                               end
+                                       end else begin
+                                       end
+                               end
+                       end
                end
        endcase
 // synthesis translate_off
@@ -9308,7 +9312,7 @@ end
 reg dummy_d_214;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_bankmachine4_cmd_payload_cas <= 1'd0;
+       soc_litedramcore_bankmachine4_req_wdata_ready <= 1'd0;
        case (vns_bankmachine4_state)
                1'd1: begin
                end
@@ -9332,7 +9336,10 @@ always @(*) begin
                                if (soc_litedramcore_bankmachine4_cmd_buffer_source_valid) begin
                                        if (soc_litedramcore_bankmachine4_row_opened) begin
                                                if (soc_litedramcore_bankmachine4_row_hit) begin
-                                                       soc_litedramcore_bankmachine4_cmd_payload_cas <= 1'd1;
+                                                       if (soc_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
+                                                               soc_litedramcore_bankmachine4_req_wdata_ready <= soc_litedramcore_bankmachine4_cmd_ready;
+                                                       end else begin
+                                                       end
                                                end else begin
                                                end
                                        end else begin
@@ -9350,19 +9357,13 @@ end
 reg dummy_d_215;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_bankmachine4_cmd_payload_ras <= 1'd0;
+       soc_litedramcore_bankmachine4_req_rdata_valid <= 1'd0;
        case (vns_bankmachine4_state)
                1'd1: begin
-                       if ((soc_litedramcore_bankmachine4_twtpcon_ready & soc_litedramcore_bankmachine4_trascon_ready)) begin
-                               soc_litedramcore_bankmachine4_cmd_payload_ras <= 1'd1;
-                       end
                end
                2'd2: begin
                end
                2'd3: begin
-                       if (soc_litedramcore_bankmachine4_trccon_ready) begin
-                               soc_litedramcore_bankmachine4_cmd_payload_ras <= 1'd1;
-                       end
                end
                3'd4: begin
                end
@@ -9375,6 +9376,21 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
+                       if (soc_litedramcore_bankmachine4_refresh_req) begin
+                       end else begin
+                               if (soc_litedramcore_bankmachine4_cmd_buffer_source_valid) begin
+                                       if (soc_litedramcore_bankmachine4_row_opened) begin
+                                               if (soc_litedramcore_bankmachine4_row_hit) begin
+                                                       if (soc_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
+                                                       end else begin
+                                                               soc_litedramcore_bankmachine4_req_rdata_valid <= soc_litedramcore_bankmachine4_cmd_ready;
+                                                       end
+                                               end else begin
+                                               end
+                                       end else begin
+                                       end
+                               end
+                       end
                end
        endcase
 // synthesis translate_off
@@ -9386,18 +9402,18 @@ end
 reg dummy_d_216;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_bankmachine4_cmd_payload_we <= 1'd0;
+       soc_litedramcore_bankmachine4_refresh_gnt <= 1'd0;
        case (vns_bankmachine4_state)
                1'd1: begin
-                       if ((soc_litedramcore_bankmachine4_twtpcon_ready & soc_litedramcore_bankmachine4_trascon_ready)) begin
-                               soc_litedramcore_bankmachine4_cmd_payload_we <= 1'd1;
-                       end
                end
                2'd2: begin
                end
                2'd3: begin
                end
                3'd4: begin
+                       if (soc_litedramcore_bankmachine4_twtpcon_ready) begin
+                               soc_litedramcore_bankmachine4_refresh_gnt <= 1'd1;
+                       end
                end
                3'd5: begin
                end
@@ -9408,21 +9424,6 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
-                       if (soc_litedramcore_bankmachine4_refresh_req) begin
-                       end else begin
-                               if (soc_litedramcore_bankmachine4_cmd_buffer_source_valid) begin
-                                       if (soc_litedramcore_bankmachine4_row_opened) begin
-                                               if (soc_litedramcore_bankmachine4_row_hit) begin
-                                                       if (soc_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
-                                                               soc_litedramcore_bankmachine4_cmd_payload_we <= 1'd1;
-                                                       end else begin
-                                                       end
-                                               end else begin
-                                               end
-                                       end else begin
-                                       end
-                               end
-                       end
                end
        endcase
 // synthesis translate_off
@@ -9434,22 +9435,21 @@ end
 reg dummy_d_217;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd0;
+       soc_litedramcore_bankmachine4_cmd_valid <= 1'd0;
        case (vns_bankmachine4_state)
                1'd1: begin
                        if ((soc_litedramcore_bankmachine4_twtpcon_ready & soc_litedramcore_bankmachine4_trascon_ready)) begin
-                               soc_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
+                               soc_litedramcore_bankmachine4_cmd_valid <= 1'd1;
                        end
                end
                2'd2: begin
                end
                2'd3: begin
                        if (soc_litedramcore_bankmachine4_trccon_ready) begin
-                               soc_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
+                               soc_litedramcore_bankmachine4_cmd_valid <= 1'd1;
                        end
                end
                3'd4: begin
-                       soc_litedramcore_bankmachine4_cmd_payload_is_cmd <= 1'd1;
                end
                3'd5: begin
                end
@@ -9460,6 +9460,18 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
+                       if (soc_litedramcore_bankmachine4_refresh_req) begin
+                       end else begin
+                               if (soc_litedramcore_bankmachine4_cmd_buffer_source_valid) begin
+                                       if (soc_litedramcore_bankmachine4_row_opened) begin
+                                               if (soc_litedramcore_bankmachine4_row_hit) begin
+                                                       soc_litedramcore_bankmachine4_cmd_valid <= 1'd1;
+                                               end else begin
+                                               end
+                                       end else begin
+                                       end
+                               end
+                       end
                end
        endcase
 // synthesis translate_off
@@ -9471,7 +9483,7 @@ end
 reg dummy_d_218;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd0;
+       soc_litedramcore_bankmachine4_row_open <= 1'd0;
        case (vns_bankmachine4_state)
                1'd1: begin
                end
@@ -9479,7 +9491,7 @@ always @(*) begin
                end
                2'd3: begin
                        if (soc_litedramcore_bankmachine4_trccon_ready) begin
-                               soc_litedramcore_bankmachine4_row_col_n_addr_sel <= 1'd1;
+                               soc_litedramcore_bankmachine4_row_open <= 1'd1;
                        end
                end
                3'd4: begin
@@ -9504,15 +9516,18 @@ end
 reg dummy_d_219;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_bankmachine4_cmd_payload_is_read <= 1'd0;
+       soc_litedramcore_bankmachine4_row_close <= 1'd0;
        case (vns_bankmachine4_state)
                1'd1: begin
+                       soc_litedramcore_bankmachine4_row_close <= 1'd1;
                end
                2'd2: begin
+                       soc_litedramcore_bankmachine4_row_close <= 1'd1;
                end
                2'd3: begin
                end
                3'd4: begin
+                       soc_litedramcore_bankmachine4_row_close <= 1'd1;
                end
                3'd5: begin
                end
@@ -9523,21 +9538,6 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
-                       if (soc_litedramcore_bankmachine4_refresh_req) begin
-                       end else begin
-                               if (soc_litedramcore_bankmachine4_cmd_buffer_source_valid) begin
-                                       if (soc_litedramcore_bankmachine4_row_opened) begin
-                                               if (soc_litedramcore_bankmachine4_row_hit) begin
-                                                       if (soc_litedramcore_bankmachine4_cmd_buffer_source_payload_we) begin
-                                                       end else begin
-                                                               soc_litedramcore_bankmachine4_cmd_payload_is_read <= 1'd1;
-                                                       end
-                                               end else begin
-                                               end
-                                       end else begin
-                                       end
-                               end
-                       end
                end
        endcase
 // synthesis translate_off
@@ -9704,7 +9704,7 @@ end
 reg dummy_d_224;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_bankmachine5_cmd_payload_is_write <= 1'd0;
+       soc_litedramcore_bankmachine5_cmd_payload_cas <= 1'd0;
        case (vns_bankmachine5_state)
                1'd1: begin
                end
@@ -9728,10 +9728,7 @@ always @(*) begin
                                if (soc_litedramcore_bankmachine5_cmd_buffer_source_valid) begin
                                        if (soc_litedramcore_bankmachine5_row_opened) begin
                                                if (soc_litedramcore_bankmachine5_row_hit) begin
-                                                       if (soc_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
-                                                               soc_litedramcore_bankmachine5_cmd_payload_is_write <= 1'd1;
-                                                       end else begin
-                                                       end
+                                                       soc_litedramcore_bankmachine5_cmd_payload_cas <= 1'd1;
                                                end else begin
                                                end
                                        end else begin
@@ -9749,13 +9746,19 @@ end
 reg dummy_d_225;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_bankmachine5_req_wdata_ready <= 1'd0;
+       soc_litedramcore_bankmachine5_cmd_payload_ras <= 1'd0;
        case (vns_bankmachine5_state)
                1'd1: begin
+                       if ((soc_litedramcore_bankmachine5_twtpcon_ready & soc_litedramcore_bankmachine5_trascon_ready)) begin
+                               soc_litedramcore_bankmachine5_cmd_payload_ras <= 1'd1;
+                       end
                end
                2'd2: begin
                end
                2'd3: begin
+                       if (soc_litedramcore_bankmachine5_trccon_ready) begin
+                               soc_litedramcore_bankmachine5_cmd_payload_ras <= 1'd1;
+                       end
                end
                3'd4: begin
                end
@@ -9768,21 +9771,6 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
-                       if (soc_litedramcore_bankmachine5_refresh_req) begin
-                       end else begin
-                               if (soc_litedramcore_bankmachine5_cmd_buffer_source_valid) begin
-                                       if (soc_litedramcore_bankmachine5_row_opened) begin
-                                               if (soc_litedramcore_bankmachine5_row_hit) begin
-                                                       if (soc_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
-                                                               soc_litedramcore_bankmachine5_req_wdata_ready <= soc_litedramcore_bankmachine5_cmd_ready;
-                                                       end else begin
-                                                       end
-                                               end else begin
-                                               end
-                                       end else begin
-                                       end
-                               end
-                       end
                end
        endcase
 // synthesis translate_off
@@ -9794,9 +9782,12 @@ end
 reg dummy_d_226;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_bankmachine5_req_rdata_valid <= 1'd0;
+       soc_litedramcore_bankmachine5_cmd_payload_we <= 1'd0;
        case (vns_bankmachine5_state)
                1'd1: begin
+                       if ((soc_litedramcore_bankmachine5_twtpcon_ready & soc_litedramcore_bankmachine5_trascon_ready)) begin
+                               soc_litedramcore_bankmachine5_cmd_payload_we <= 1'd1;
+                       end
                end
                2'd2: begin
                end
@@ -9819,8 +9810,8 @@ always @(*) begin
                                        if (soc_litedramcore_bankmachine5_row_opened) begin
                                                if (soc_litedramcore_bankmachine5_row_hit) begin
                                                        if (soc_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
+                                                               soc_litedramcore_bankmachine5_cmd_payload_we <= 1'd1;
                                                        end else begin
-                                                               soc_litedramcore_bankmachine5_req_rdata_valid <= soc_litedramcore_bankmachine5_cmd_ready;
                                                        end
                                                end else begin
                                                end
@@ -9872,18 +9863,22 @@ end
 reg dummy_d_228;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_bankmachine5_refresh_gnt <= 1'd0;
+       soc_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd0;
        case (vns_bankmachine5_state)
                1'd1: begin
+                       if ((soc_litedramcore_bankmachine5_twtpcon_ready & soc_litedramcore_bankmachine5_trascon_ready)) begin
+                               soc_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
+                       end
                end
                2'd2: begin
                end
                2'd3: begin
+                       if (soc_litedramcore_bankmachine5_trccon_ready) begin
+                               soc_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
+                       end
                end
                3'd4: begin
-                       if (soc_litedramcore_bankmachine5_twtpcon_ready) begin
-                               soc_litedramcore_bankmachine5_refresh_gnt <= 1'd1;
-                       end
+                       soc_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
                end
                3'd5: begin
                end
@@ -9905,19 +9900,13 @@ end
 reg dummy_d_229;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_bankmachine5_cmd_valid <= 1'd0;
+       soc_litedramcore_bankmachine5_cmd_payload_is_read <= 1'd0;
        case (vns_bankmachine5_state)
                1'd1: begin
-                       if ((soc_litedramcore_bankmachine5_twtpcon_ready & soc_litedramcore_bankmachine5_trascon_ready)) begin
-                               soc_litedramcore_bankmachine5_cmd_valid <= 1'd1;
-                       end
                end
                2'd2: begin
                end
                2'd3: begin
-                       if (soc_litedramcore_bankmachine5_trccon_ready) begin
-                               soc_litedramcore_bankmachine5_cmd_valid <= 1'd1;
-                       end
                end
                3'd4: begin
                end
@@ -9935,7 +9924,10 @@ always @(*) begin
                                if (soc_litedramcore_bankmachine5_cmd_buffer_source_valid) begin
                                        if (soc_litedramcore_bankmachine5_row_opened) begin
                                                if (soc_litedramcore_bankmachine5_row_hit) begin
-                                                       soc_litedramcore_bankmachine5_cmd_valid <= 1'd1;
+                                                       if (soc_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
+                                                       end else begin
+                                                               soc_litedramcore_bankmachine5_cmd_payload_is_read <= 1'd1;
+                                                       end
                                                end else begin
                                                end
                                        end else begin
@@ -9953,16 +9945,13 @@ end
 reg dummy_d_230;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_bankmachine5_row_open <= 1'd0;
+       soc_litedramcore_bankmachine5_cmd_payload_is_write <= 1'd0;
        case (vns_bankmachine5_state)
                1'd1: begin
                end
                2'd2: begin
                end
                2'd3: begin
-                       if (soc_litedramcore_bankmachine5_trccon_ready) begin
-                               soc_litedramcore_bankmachine5_row_open <= 1'd1;
-                       end
                end
                3'd4: begin
                end
@@ -9975,6 +9964,21 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
+                       if (soc_litedramcore_bankmachine5_refresh_req) begin
+                       end else begin
+                               if (soc_litedramcore_bankmachine5_cmd_buffer_source_valid) begin
+                                       if (soc_litedramcore_bankmachine5_row_opened) begin
+                                               if (soc_litedramcore_bankmachine5_row_hit) begin
+                                                       if (soc_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
+                                                               soc_litedramcore_bankmachine5_cmd_payload_is_write <= 1'd1;
+                                                       end else begin
+                                                       end
+                                               end else begin
+                                               end
+                                       end else begin
+                                       end
+                               end
+                       end
                end
        endcase
 // synthesis translate_off
@@ -9986,18 +9990,15 @@ end
 reg dummy_d_231;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_bankmachine5_row_close <= 1'd0;
+       soc_litedramcore_bankmachine5_req_wdata_ready <= 1'd0;
        case (vns_bankmachine5_state)
                1'd1: begin
-                       soc_litedramcore_bankmachine5_row_close <= 1'd1;
                end
                2'd2: begin
-                       soc_litedramcore_bankmachine5_row_close <= 1'd1;
                end
                2'd3: begin
                end
                3'd4: begin
-                       soc_litedramcore_bankmachine5_row_close <= 1'd1;
                end
                3'd5: begin
                end
@@ -10008,6 +10009,21 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
+                       if (soc_litedramcore_bankmachine5_refresh_req) begin
+                       end else begin
+                               if (soc_litedramcore_bankmachine5_cmd_buffer_source_valid) begin
+                                       if (soc_litedramcore_bankmachine5_row_opened) begin
+                                               if (soc_litedramcore_bankmachine5_row_hit) begin
+                                                       if (soc_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
+                                                               soc_litedramcore_bankmachine5_req_wdata_ready <= soc_litedramcore_bankmachine5_cmd_ready;
+                                                       end else begin
+                                                       end
+                                               end else begin
+                                               end
+                                       end else begin
+                                       end
+                               end
+                       end
                end
        endcase
 // synthesis translate_off
@@ -10019,7 +10035,7 @@ end
 reg dummy_d_232;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_bankmachine5_cmd_payload_cas <= 1'd0;
+       soc_litedramcore_bankmachine5_req_rdata_valid <= 1'd0;
        case (vns_bankmachine5_state)
                1'd1: begin
                end
@@ -10043,7 +10059,10 @@ always @(*) begin
                                if (soc_litedramcore_bankmachine5_cmd_buffer_source_valid) begin
                                        if (soc_litedramcore_bankmachine5_row_opened) begin
                                                if (soc_litedramcore_bankmachine5_row_hit) begin
-                                                       soc_litedramcore_bankmachine5_cmd_payload_cas <= 1'd1;
+                                                       if (soc_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
+                                                       end else begin
+                                                               soc_litedramcore_bankmachine5_req_rdata_valid <= soc_litedramcore_bankmachine5_cmd_ready;
+                                                       end
                                                end else begin
                                                end
                                        end else begin
@@ -10061,21 +10080,18 @@ end
 reg dummy_d_233;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_bankmachine5_cmd_payload_ras <= 1'd0;
+       soc_litedramcore_bankmachine5_refresh_gnt <= 1'd0;
        case (vns_bankmachine5_state)
                1'd1: begin
-                       if ((soc_litedramcore_bankmachine5_twtpcon_ready & soc_litedramcore_bankmachine5_trascon_ready)) begin
-                               soc_litedramcore_bankmachine5_cmd_payload_ras <= 1'd1;
-                       end
                end
                2'd2: begin
                end
                2'd3: begin
-                       if (soc_litedramcore_bankmachine5_trccon_ready) begin
-                               soc_litedramcore_bankmachine5_cmd_payload_ras <= 1'd1;
-                       end
                end
                3'd4: begin
+                       if (soc_litedramcore_bankmachine5_twtpcon_ready) begin
+                               soc_litedramcore_bankmachine5_refresh_gnt <= 1'd1;
+                       end
                end
                3'd5: begin
                end
@@ -10097,16 +10113,19 @@ end
 reg dummy_d_234;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_bankmachine5_cmd_payload_we <= 1'd0;
+       soc_litedramcore_bankmachine5_cmd_valid <= 1'd0;
        case (vns_bankmachine5_state)
                1'd1: begin
                        if ((soc_litedramcore_bankmachine5_twtpcon_ready & soc_litedramcore_bankmachine5_trascon_ready)) begin
-                               soc_litedramcore_bankmachine5_cmd_payload_we <= 1'd1;
+                               soc_litedramcore_bankmachine5_cmd_valid <= 1'd1;
                        end
                end
                2'd2: begin
                end
                2'd3: begin
+                       if (soc_litedramcore_bankmachine5_trccon_ready) begin
+                               soc_litedramcore_bankmachine5_cmd_valid <= 1'd1;
+                       end
                end
                3'd4: begin
                end
@@ -10124,10 +10143,7 @@ always @(*) begin
                                if (soc_litedramcore_bankmachine5_cmd_buffer_source_valid) begin
                                        if (soc_litedramcore_bankmachine5_row_opened) begin
                                                if (soc_litedramcore_bankmachine5_row_hit) begin
-                                                       if (soc_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
-                                                               soc_litedramcore_bankmachine5_cmd_payload_we <= 1'd1;
-                                                       end else begin
-                                                       end
+                                                       soc_litedramcore_bankmachine5_cmd_valid <= 1'd1;
                                                end else begin
                                                end
                                        end else begin
@@ -10145,22 +10161,18 @@ end
 reg dummy_d_235;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd0;
+       soc_litedramcore_bankmachine5_row_open <= 1'd0;
        case (vns_bankmachine5_state)
                1'd1: begin
-                       if ((soc_litedramcore_bankmachine5_twtpcon_ready & soc_litedramcore_bankmachine5_trascon_ready)) begin
-                               soc_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
-                       end
                end
                2'd2: begin
                end
                2'd3: begin
                        if (soc_litedramcore_bankmachine5_trccon_ready) begin
-                               soc_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
+                               soc_litedramcore_bankmachine5_row_open <= 1'd1;
                        end
                end
                3'd4: begin
-                       soc_litedramcore_bankmachine5_cmd_payload_is_cmd <= 1'd1;
                end
                3'd5: begin
                end
@@ -10182,15 +10194,18 @@ end
 reg dummy_d_236;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_bankmachine5_cmd_payload_is_read <= 1'd0;
+       soc_litedramcore_bankmachine5_row_close <= 1'd0;
        case (vns_bankmachine5_state)
                1'd1: begin
+                       soc_litedramcore_bankmachine5_row_close <= 1'd1;
                end
                2'd2: begin
+                       soc_litedramcore_bankmachine5_row_close <= 1'd1;
                end
                2'd3: begin
                end
                3'd4: begin
+                       soc_litedramcore_bankmachine5_row_close <= 1'd1;
                end
                3'd5: begin
                end
@@ -10201,21 +10216,6 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
-                       if (soc_litedramcore_bankmachine5_refresh_req) begin
-                       end else begin
-                               if (soc_litedramcore_bankmachine5_cmd_buffer_source_valid) begin
-                                       if (soc_litedramcore_bankmachine5_row_opened) begin
-                                               if (soc_litedramcore_bankmachine5_row_hit) begin
-                                                       if (soc_litedramcore_bankmachine5_cmd_buffer_source_payload_we) begin
-                                                       end else begin
-                                                               soc_litedramcore_bankmachine5_cmd_payload_is_read <= 1'd1;
-                                                       end
-                                               end else begin
-                                               end
-                                       end else begin
-                                       end
-                               end
-                       end
                end
        endcase
 // synthesis translate_off
@@ -10382,7 +10382,7 @@ end
 reg dummy_d_241;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_bankmachine6_cmd_payload_is_write <= 1'd0;
+       soc_litedramcore_bankmachine6_cmd_payload_cas <= 1'd0;
        case (vns_bankmachine6_state)
                1'd1: begin
                end
@@ -10406,10 +10406,7 @@ always @(*) begin
                                if (soc_litedramcore_bankmachine6_cmd_buffer_source_valid) begin
                                        if (soc_litedramcore_bankmachine6_row_opened) begin
                                                if (soc_litedramcore_bankmachine6_row_hit) begin
-                                                       if (soc_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
-                                                               soc_litedramcore_bankmachine6_cmd_payload_is_write <= 1'd1;
-                                                       end else begin
-                                                       end
+                                                       soc_litedramcore_bankmachine6_cmd_payload_cas <= 1'd1;
                                                end else begin
                                                end
                                        end else begin
@@ -10427,13 +10424,19 @@ end
 reg dummy_d_242;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_bankmachine6_req_wdata_ready <= 1'd0;
+       soc_litedramcore_bankmachine6_cmd_payload_ras <= 1'd0;
        case (vns_bankmachine6_state)
                1'd1: begin
+                       if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin
+                               soc_litedramcore_bankmachine6_cmd_payload_ras <= 1'd1;
+                       end
                end
                2'd2: begin
                end
                2'd3: begin
+                       if (soc_litedramcore_bankmachine6_trccon_ready) begin
+                               soc_litedramcore_bankmachine6_cmd_payload_ras <= 1'd1;
+                       end
                end
                3'd4: begin
                end
@@ -10446,21 +10449,6 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
-                       if (soc_litedramcore_bankmachine6_refresh_req) begin
-                       end else begin
-                               if (soc_litedramcore_bankmachine6_cmd_buffer_source_valid) begin
-                                       if (soc_litedramcore_bankmachine6_row_opened) begin
-                                               if (soc_litedramcore_bankmachine6_row_hit) begin
-                                                       if (soc_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
-                                                               soc_litedramcore_bankmachine6_req_wdata_ready <= soc_litedramcore_bankmachine6_cmd_ready;
-                                                       end else begin
-                                                       end
-                                               end else begin
-                                               end
-                                       end else begin
-                                       end
-                               end
-                       end
                end
        endcase
 // synthesis translate_off
@@ -10472,9 +10460,12 @@ end
 reg dummy_d_243;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_bankmachine6_req_rdata_valid <= 1'd0;
+       soc_litedramcore_bankmachine6_cmd_payload_we <= 1'd0;
        case (vns_bankmachine6_state)
                1'd1: begin
+                       if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin
+                               soc_litedramcore_bankmachine6_cmd_payload_we <= 1'd1;
+                       end
                end
                2'd2: begin
                end
@@ -10497,8 +10488,8 @@ always @(*) begin
                                        if (soc_litedramcore_bankmachine6_row_opened) begin
                                                if (soc_litedramcore_bankmachine6_row_hit) begin
                                                        if (soc_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
+                                                               soc_litedramcore_bankmachine6_cmd_payload_we <= 1'd1;
                                                        end else begin
-                                                               soc_litedramcore_bankmachine6_req_rdata_valid <= soc_litedramcore_bankmachine6_cmd_ready;
                                                        end
                                                end else begin
                                                end
@@ -10517,18 +10508,18 @@ end
 reg dummy_d_244;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_bankmachine6_refresh_gnt <= 1'd0;
+       soc_litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0;
        case (vns_bankmachine6_state)
                1'd1: begin
                end
                2'd2: begin
                end
                2'd3: begin
+                       if (soc_litedramcore_bankmachine6_trccon_ready) begin
+                               soc_litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd1;
+                       end
                end
                3'd4: begin
-                       if (soc_litedramcore_bankmachine6_twtpcon_ready) begin
-                               soc_litedramcore_bankmachine6_refresh_gnt <= 1'd1;
-                       end
                end
                3'd5: begin
                end
@@ -10550,21 +10541,22 @@ end
 reg dummy_d_245;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_bankmachine6_cmd_valid <= 1'd0;
+       soc_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0;
        case (vns_bankmachine6_state)
                1'd1: begin
                        if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin
-                               soc_litedramcore_bankmachine6_cmd_valid <= 1'd1;
+                               soc_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
                        end
                end
                2'd2: begin
                end
                2'd3: begin
                        if (soc_litedramcore_bankmachine6_trccon_ready) begin
-                               soc_litedramcore_bankmachine6_cmd_valid <= 1'd1;
+                               soc_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
                        end
                end
                3'd4: begin
+                       soc_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
                end
                3'd5: begin
                end
@@ -10575,18 +10567,6 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
-                       if (soc_litedramcore_bankmachine6_refresh_req) begin
-                       end else begin
-                               if (soc_litedramcore_bankmachine6_cmd_buffer_source_valid) begin
-                                       if (soc_litedramcore_bankmachine6_row_opened) begin
-                                               if (soc_litedramcore_bankmachine6_row_hit) begin
-                                                       soc_litedramcore_bankmachine6_cmd_valid <= 1'd1;
-                                               end else begin
-                                               end
-                                       end else begin
-                                       end
-                               end
-                       end
                end
        endcase
 // synthesis translate_off
@@ -10598,16 +10578,13 @@ end
 reg dummy_d_246;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd0;
+       soc_litedramcore_bankmachine6_cmd_payload_is_read <= 1'd0;
        case (vns_bankmachine6_state)
                1'd1: begin
                end
                2'd2: begin
                end
                2'd3: begin
-                       if (soc_litedramcore_bankmachine6_trccon_ready) begin
-                               soc_litedramcore_bankmachine6_row_col_n_addr_sel <= 1'd1;
-                       end
                end
                3'd4: begin
                end
@@ -10620,6 +10597,21 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
+                       if (soc_litedramcore_bankmachine6_refresh_req) begin
+                       end else begin
+                               if (soc_litedramcore_bankmachine6_cmd_buffer_source_valid) begin
+                                       if (soc_litedramcore_bankmachine6_row_opened) begin
+                                               if (soc_litedramcore_bankmachine6_row_hit) begin
+                                                       if (soc_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
+                                                       end else begin
+                                                               soc_litedramcore_bankmachine6_cmd_payload_is_read <= 1'd1;
+                                                       end
+                                               end else begin
+                                               end
+                                       end else begin
+                                       end
+                               end
+                       end
                end
        endcase
 // synthesis translate_off
@@ -10631,16 +10623,13 @@ end
 reg dummy_d_247;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_bankmachine6_row_open <= 1'd0;
+       soc_litedramcore_bankmachine6_cmd_payload_is_write <= 1'd0;
        case (vns_bankmachine6_state)
                1'd1: begin
                end
                2'd2: begin
                end
                2'd3: begin
-                       if (soc_litedramcore_bankmachine6_trccon_ready) begin
-                               soc_litedramcore_bankmachine6_row_open <= 1'd1;
-                       end
                end
                3'd4: begin
                end
@@ -10653,6 +10642,21 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
+                       if (soc_litedramcore_bankmachine6_refresh_req) begin
+                       end else begin
+                               if (soc_litedramcore_bankmachine6_cmd_buffer_source_valid) begin
+                                       if (soc_litedramcore_bankmachine6_row_opened) begin
+                                               if (soc_litedramcore_bankmachine6_row_hit) begin
+                                                       if (soc_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
+                                                               soc_litedramcore_bankmachine6_cmd_payload_is_write <= 1'd1;
+                                                       end else begin
+                                                       end
+                                               end else begin
+                                               end
+                                       end else begin
+                                       end
+                               end
+                       end
                end
        endcase
 // synthesis translate_off
@@ -10664,18 +10668,15 @@ end
 reg dummy_d_248;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_bankmachine6_row_close <= 1'd0;
+       soc_litedramcore_bankmachine6_req_wdata_ready <= 1'd0;
        case (vns_bankmachine6_state)
                1'd1: begin
-                       soc_litedramcore_bankmachine6_row_close <= 1'd1;
                end
                2'd2: begin
-                       soc_litedramcore_bankmachine6_row_close <= 1'd1;
                end
                2'd3: begin
                end
                3'd4: begin
-                       soc_litedramcore_bankmachine6_row_close <= 1'd1;
                end
                3'd5: begin
                end
@@ -10686,6 +10687,21 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
+                       if (soc_litedramcore_bankmachine6_refresh_req) begin
+                       end else begin
+                               if (soc_litedramcore_bankmachine6_cmd_buffer_source_valid) begin
+                                       if (soc_litedramcore_bankmachine6_row_opened) begin
+                                               if (soc_litedramcore_bankmachine6_row_hit) begin
+                                                       if (soc_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
+                                                               soc_litedramcore_bankmachine6_req_wdata_ready <= soc_litedramcore_bankmachine6_cmd_ready;
+                                                       end else begin
+                                                       end
+                                               end else begin
+                                               end
+                                       end else begin
+                                       end
+                               end
+                       end
                end
        endcase
 // synthesis translate_off
@@ -10697,7 +10713,7 @@ end
 reg dummy_d_249;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_bankmachine6_cmd_payload_cas <= 1'd0;
+       soc_litedramcore_bankmachine6_req_rdata_valid <= 1'd0;
        case (vns_bankmachine6_state)
                1'd1: begin
                end
@@ -10721,7 +10737,10 @@ always @(*) begin
                                if (soc_litedramcore_bankmachine6_cmd_buffer_source_valid) begin
                                        if (soc_litedramcore_bankmachine6_row_opened) begin
                                                if (soc_litedramcore_bankmachine6_row_hit) begin
-                                                       soc_litedramcore_bankmachine6_cmd_payload_cas <= 1'd1;
+                                                       if (soc_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
+                                                       end else begin
+                                                               soc_litedramcore_bankmachine6_req_rdata_valid <= soc_litedramcore_bankmachine6_cmd_ready;
+                                                       end
                                                end else begin
                                                end
                                        end else begin
@@ -10739,21 +10758,18 @@ end
 reg dummy_d_250;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_bankmachine6_cmd_payload_ras <= 1'd0;
+       soc_litedramcore_bankmachine6_refresh_gnt <= 1'd0;
        case (vns_bankmachine6_state)
                1'd1: begin
-                       if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin
-                               soc_litedramcore_bankmachine6_cmd_payload_ras <= 1'd1;
-                       end
                end
                2'd2: begin
                end
                2'd3: begin
-                       if (soc_litedramcore_bankmachine6_trccon_ready) begin
-                               soc_litedramcore_bankmachine6_cmd_payload_ras <= 1'd1;
-                       end
                end
                3'd4: begin
+                       if (soc_litedramcore_bankmachine6_twtpcon_ready) begin
+                               soc_litedramcore_bankmachine6_refresh_gnt <= 1'd1;
+                       end
                end
                3'd5: begin
                end
@@ -10775,16 +10791,19 @@ end
 reg dummy_d_251;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_bankmachine6_cmd_payload_we <= 1'd0;
+       soc_litedramcore_bankmachine6_cmd_valid <= 1'd0;
        case (vns_bankmachine6_state)
                1'd1: begin
                        if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin
-                               soc_litedramcore_bankmachine6_cmd_payload_we <= 1'd1;
+                               soc_litedramcore_bankmachine6_cmd_valid <= 1'd1;
                        end
                end
                2'd2: begin
                end
                2'd3: begin
+                       if (soc_litedramcore_bankmachine6_trccon_ready) begin
+                               soc_litedramcore_bankmachine6_cmd_valid <= 1'd1;
+                       end
                end
                3'd4: begin
                end
@@ -10802,10 +10821,7 @@ always @(*) begin
                                if (soc_litedramcore_bankmachine6_cmd_buffer_source_valid) begin
                                        if (soc_litedramcore_bankmachine6_row_opened) begin
                                                if (soc_litedramcore_bankmachine6_row_hit) begin
-                                                       if (soc_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
-                                                               soc_litedramcore_bankmachine6_cmd_payload_we <= 1'd1;
-                                                       end else begin
-                                                       end
+                                                       soc_litedramcore_bankmachine6_cmd_valid <= 1'd1;
                                                end else begin
                                                end
                                        end else begin
@@ -10823,22 +10839,18 @@ end
 reg dummy_d_252;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd0;
+       soc_litedramcore_bankmachine6_row_open <= 1'd0;
        case (vns_bankmachine6_state)
                1'd1: begin
-                       if ((soc_litedramcore_bankmachine6_twtpcon_ready & soc_litedramcore_bankmachine6_trascon_ready)) begin
-                               soc_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
-                       end
                end
                2'd2: begin
                end
                2'd3: begin
                        if (soc_litedramcore_bankmachine6_trccon_ready) begin
-                               soc_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
+                               soc_litedramcore_bankmachine6_row_open <= 1'd1;
                        end
                end
                3'd4: begin
-                       soc_litedramcore_bankmachine6_cmd_payload_is_cmd <= 1'd1;
                end
                3'd5: begin
                end
@@ -10860,15 +10872,18 @@ end
 reg dummy_d_253;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_bankmachine6_cmd_payload_is_read <= 1'd0;
+       soc_litedramcore_bankmachine6_row_close <= 1'd0;
        case (vns_bankmachine6_state)
                1'd1: begin
+                       soc_litedramcore_bankmachine6_row_close <= 1'd1;
                end
                2'd2: begin
+                       soc_litedramcore_bankmachine6_row_close <= 1'd1;
                end
                2'd3: begin
                end
                3'd4: begin
+                       soc_litedramcore_bankmachine6_row_close <= 1'd1;
                end
                3'd5: begin
                end
@@ -10879,21 +10894,6 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
-                       if (soc_litedramcore_bankmachine6_refresh_req) begin
-                       end else begin
-                               if (soc_litedramcore_bankmachine6_cmd_buffer_source_valid) begin
-                                       if (soc_litedramcore_bankmachine6_row_opened) begin
-                                               if (soc_litedramcore_bankmachine6_row_hit) begin
-                                                       if (soc_litedramcore_bankmachine6_cmd_buffer_source_payload_we) begin
-                                                       end else begin
-                                                               soc_litedramcore_bankmachine6_cmd_payload_is_read <= 1'd1;
-                                                       end
-                                               end else begin
-                                               end
-                                       end else begin
-                                       end
-                               end
-                       end
                end
        endcase
 // synthesis translate_off
@@ -11060,7 +11060,7 @@ end
 reg dummy_d_258;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_bankmachine7_cmd_payload_is_write <= 1'd0;
+       soc_litedramcore_bankmachine7_cmd_payload_cas <= 1'd0;
        case (vns_bankmachine7_state)
                1'd1: begin
                end
@@ -11084,10 +11084,7 @@ always @(*) begin
                                if (soc_litedramcore_bankmachine7_cmd_buffer_source_valid) begin
                                        if (soc_litedramcore_bankmachine7_row_opened) begin
                                                if (soc_litedramcore_bankmachine7_row_hit) begin
-                                                       if (soc_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
-                                                               soc_litedramcore_bankmachine7_cmd_payload_is_write <= 1'd1;
-                                                       end else begin
-                                                       end
+                                                       soc_litedramcore_bankmachine7_cmd_payload_cas <= 1'd1;
                                                end else begin
                                                end
                                        end else begin
@@ -11105,13 +11102,19 @@ end
 reg dummy_d_259;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_bankmachine7_req_wdata_ready <= 1'd0;
+       soc_litedramcore_bankmachine7_cmd_payload_ras <= 1'd0;
        case (vns_bankmachine7_state)
                1'd1: begin
+                       if ((soc_litedramcore_bankmachine7_twtpcon_ready & soc_litedramcore_bankmachine7_trascon_ready)) begin
+                               soc_litedramcore_bankmachine7_cmd_payload_ras <= 1'd1;
+                       end
                end
                2'd2: begin
                end
                2'd3: begin
+                       if (soc_litedramcore_bankmachine7_trccon_ready) begin
+                               soc_litedramcore_bankmachine7_cmd_payload_ras <= 1'd1;
+                       end
                end
                3'd4: begin
                end
@@ -11124,21 +11127,6 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
-                       if (soc_litedramcore_bankmachine7_refresh_req) begin
-                       end else begin
-                               if (soc_litedramcore_bankmachine7_cmd_buffer_source_valid) begin
-                                       if (soc_litedramcore_bankmachine7_row_opened) begin
-                                               if (soc_litedramcore_bankmachine7_row_hit) begin
-                                                       if (soc_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
-                                                               soc_litedramcore_bankmachine7_req_wdata_ready <= soc_litedramcore_bankmachine7_cmd_ready;
-                                                       end else begin
-                                                       end
-                                               end else begin
-                                               end
-                                       end else begin
-                                       end
-                               end
-                       end
                end
        endcase
 // synthesis translate_off
@@ -11150,9 +11138,12 @@ end
 reg dummy_d_260;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_bankmachine7_req_rdata_valid <= 1'd0;
+       soc_litedramcore_bankmachine7_cmd_payload_we <= 1'd0;
        case (vns_bankmachine7_state)
                1'd1: begin
+                       if ((soc_litedramcore_bankmachine7_twtpcon_ready & soc_litedramcore_bankmachine7_trascon_ready)) begin
+                               soc_litedramcore_bankmachine7_cmd_payload_we <= 1'd1;
+                       end
                end
                2'd2: begin
                end
@@ -11175,8 +11166,8 @@ always @(*) begin
                                        if (soc_litedramcore_bankmachine7_row_opened) begin
                                                if (soc_litedramcore_bankmachine7_row_hit) begin
                                                        if (soc_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
+                                                               soc_litedramcore_bankmachine7_cmd_payload_we <= 1'd1;
                                                        end else begin
-                                                               soc_litedramcore_bankmachine7_req_rdata_valid <= soc_litedramcore_bankmachine7_cmd_ready;
                                                        end
                                                end else begin
                                                end
@@ -11195,18 +11186,18 @@ end
 reg dummy_d_261;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_bankmachine7_refresh_gnt <= 1'd0;
+       soc_litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0;
        case (vns_bankmachine7_state)
                1'd1: begin
                end
                2'd2: begin
                end
                2'd3: begin
+                       if (soc_litedramcore_bankmachine7_trccon_ready) begin
+                               soc_litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1;
+                       end
                end
                3'd4: begin
-                       if (soc_litedramcore_bankmachine7_twtpcon_ready) begin
-                               soc_litedramcore_bankmachine7_refresh_gnt <= 1'd1;
-                       end
                end
                3'd5: begin
                end
@@ -11228,21 +11219,22 @@ end
 reg dummy_d_262;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_bankmachine7_cmd_valid <= 1'd0;
+       soc_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd0;
        case (vns_bankmachine7_state)
                1'd1: begin
                        if ((soc_litedramcore_bankmachine7_twtpcon_ready & soc_litedramcore_bankmachine7_trascon_ready)) begin
-                               soc_litedramcore_bankmachine7_cmd_valid <= 1'd1;
+                               soc_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
                        end
                end
                2'd2: begin
                end
                2'd3: begin
                        if (soc_litedramcore_bankmachine7_trccon_ready) begin
-                               soc_litedramcore_bankmachine7_cmd_valid <= 1'd1;
+                               soc_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
                        end
                end
                3'd4: begin
+                       soc_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
                end
                3'd5: begin
                end
@@ -11253,18 +11245,6 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
-                       if (soc_litedramcore_bankmachine7_refresh_req) begin
-                       end else begin
-                               if (soc_litedramcore_bankmachine7_cmd_buffer_source_valid) begin
-                                       if (soc_litedramcore_bankmachine7_row_opened) begin
-                                               if (soc_litedramcore_bankmachine7_row_hit) begin
-                                                       soc_litedramcore_bankmachine7_cmd_valid <= 1'd1;
-                                               end else begin
-                                               end
-                                       end else begin
-                                       end
-                               end
-                       end
                end
        endcase
 // synthesis translate_off
@@ -11276,16 +11256,13 @@ end
 reg dummy_d_263;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd0;
+       soc_litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0;
        case (vns_bankmachine7_state)
                1'd1: begin
                end
                2'd2: begin
                end
                2'd3: begin
-                       if (soc_litedramcore_bankmachine7_trccon_ready) begin
-                               soc_litedramcore_bankmachine7_row_col_n_addr_sel <= 1'd1;
-                       end
                end
                3'd4: begin
                end
@@ -11298,6 +11275,21 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
+                       if (soc_litedramcore_bankmachine7_refresh_req) begin
+                       end else begin
+                               if (soc_litedramcore_bankmachine7_cmd_buffer_source_valid) begin
+                                       if (soc_litedramcore_bankmachine7_row_opened) begin
+                                               if (soc_litedramcore_bankmachine7_row_hit) begin
+                                                       if (soc_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
+                                                       end else begin
+                                                               soc_litedramcore_bankmachine7_cmd_payload_is_read <= 1'd1;
+                                                       end
+                                               end else begin
+                                               end
+                                       end else begin
+                                       end
+                               end
+                       end
                end
        endcase
 // synthesis translate_off
@@ -11309,16 +11301,13 @@ end
 reg dummy_d_264;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_bankmachine7_row_open <= 1'd0;
+       soc_litedramcore_bankmachine7_cmd_payload_is_write <= 1'd0;
        case (vns_bankmachine7_state)
                1'd1: begin
                end
                2'd2: begin
                end
                2'd3: begin
-                       if (soc_litedramcore_bankmachine7_trccon_ready) begin
-                               soc_litedramcore_bankmachine7_row_open <= 1'd1;
-                       end
                end
                3'd4: begin
                end
@@ -11331,6 +11320,21 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
+                       if (soc_litedramcore_bankmachine7_refresh_req) begin
+                       end else begin
+                               if (soc_litedramcore_bankmachine7_cmd_buffer_source_valid) begin
+                                       if (soc_litedramcore_bankmachine7_row_opened) begin
+                                               if (soc_litedramcore_bankmachine7_row_hit) begin
+                                                       if (soc_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
+                                                               soc_litedramcore_bankmachine7_cmd_payload_is_write <= 1'd1;
+                                                       end else begin
+                                                       end
+                                               end else begin
+                                               end
+                                       end else begin
+                                       end
+                               end
+                       end
                end
        endcase
 // synthesis translate_off
@@ -11342,18 +11346,15 @@ end
 reg dummy_d_265;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_bankmachine7_row_close <= 1'd0;
+       soc_litedramcore_bankmachine7_req_wdata_ready <= 1'd0;
        case (vns_bankmachine7_state)
                1'd1: begin
-                       soc_litedramcore_bankmachine7_row_close <= 1'd1;
                end
                2'd2: begin
-                       soc_litedramcore_bankmachine7_row_close <= 1'd1;
                end
                2'd3: begin
                end
                3'd4: begin
-                       soc_litedramcore_bankmachine7_row_close <= 1'd1;
                end
                3'd5: begin
                end
@@ -11364,6 +11365,21 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
+                       if (soc_litedramcore_bankmachine7_refresh_req) begin
+                       end else begin
+                               if (soc_litedramcore_bankmachine7_cmd_buffer_source_valid) begin
+                                       if (soc_litedramcore_bankmachine7_row_opened) begin
+                                               if (soc_litedramcore_bankmachine7_row_hit) begin
+                                                       if (soc_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
+                                                               soc_litedramcore_bankmachine7_req_wdata_ready <= soc_litedramcore_bankmachine7_cmd_ready;
+                                                       end else begin
+                                                       end
+                                               end else begin
+                                               end
+                                       end else begin
+                                       end
+                               end
+                       end
                end
        endcase
 // synthesis translate_off
@@ -11375,7 +11391,7 @@ end
 reg dummy_d_266;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_bankmachine7_cmd_payload_cas <= 1'd0;
+       soc_litedramcore_bankmachine7_req_rdata_valid <= 1'd0;
        case (vns_bankmachine7_state)
                1'd1: begin
                end
@@ -11399,7 +11415,10 @@ always @(*) begin
                                if (soc_litedramcore_bankmachine7_cmd_buffer_source_valid) begin
                                        if (soc_litedramcore_bankmachine7_row_opened) begin
                                                if (soc_litedramcore_bankmachine7_row_hit) begin
-                                                       soc_litedramcore_bankmachine7_cmd_payload_cas <= 1'd1;
+                                                       if (soc_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
+                                                       end else begin
+                                                               soc_litedramcore_bankmachine7_req_rdata_valid <= soc_litedramcore_bankmachine7_cmd_ready;
+                                                       end
                                                end else begin
                                                end
                                        end else begin
@@ -11417,21 +11436,18 @@ end
 reg dummy_d_267;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_bankmachine7_cmd_payload_ras <= 1'd0;
+       soc_litedramcore_bankmachine7_refresh_gnt <= 1'd0;
        case (vns_bankmachine7_state)
                1'd1: begin
-                       if ((soc_litedramcore_bankmachine7_twtpcon_ready & soc_litedramcore_bankmachine7_trascon_ready)) begin
-                               soc_litedramcore_bankmachine7_cmd_payload_ras <= 1'd1;
-                       end
                end
                2'd2: begin
                end
                2'd3: begin
-                       if (soc_litedramcore_bankmachine7_trccon_ready) begin
-                               soc_litedramcore_bankmachine7_cmd_payload_ras <= 1'd1;
-                       end
                end
                3'd4: begin
+                       if (soc_litedramcore_bankmachine7_twtpcon_ready) begin
+                               soc_litedramcore_bankmachine7_refresh_gnt <= 1'd1;
+                       end
                end
                3'd5: begin
                end
@@ -11453,16 +11469,19 @@ end
 reg dummy_d_268;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_bankmachine7_cmd_payload_we <= 1'd0;
+       soc_litedramcore_bankmachine7_cmd_valid <= 1'd0;
        case (vns_bankmachine7_state)
                1'd1: begin
                        if ((soc_litedramcore_bankmachine7_twtpcon_ready & soc_litedramcore_bankmachine7_trascon_ready)) begin
-                               soc_litedramcore_bankmachine7_cmd_payload_we <= 1'd1;
+                               soc_litedramcore_bankmachine7_cmd_valid <= 1'd1;
                        end
                end
                2'd2: begin
                end
                2'd3: begin
+                       if (soc_litedramcore_bankmachine7_trccon_ready) begin
+                               soc_litedramcore_bankmachine7_cmd_valid <= 1'd1;
+                       end
                end
                3'd4: begin
                end
@@ -11480,10 +11499,7 @@ always @(*) begin
                                if (soc_litedramcore_bankmachine7_cmd_buffer_source_valid) begin
                                        if (soc_litedramcore_bankmachine7_row_opened) begin
                                                if (soc_litedramcore_bankmachine7_row_hit) begin
-                                                       if (soc_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
-                                                               soc_litedramcore_bankmachine7_cmd_payload_we <= 1'd1;
-                                                       end else begin
-                                                       end
+                                                       soc_litedramcore_bankmachine7_cmd_valid <= 1'd1;
                                                end else begin
                                                end
                                        end else begin
@@ -11501,22 +11517,18 @@ end
 reg dummy_d_269;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd0;
+       soc_litedramcore_bankmachine7_row_open <= 1'd0;
        case (vns_bankmachine7_state)
                1'd1: begin
-                       if ((soc_litedramcore_bankmachine7_twtpcon_ready & soc_litedramcore_bankmachine7_trascon_ready)) begin
-                               soc_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
-                       end
                end
                2'd2: begin
                end
                2'd3: begin
                        if (soc_litedramcore_bankmachine7_trccon_ready) begin
-                               soc_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
+                               soc_litedramcore_bankmachine7_row_open <= 1'd1;
                        end
                end
                3'd4: begin
-                       soc_litedramcore_bankmachine7_cmd_payload_is_cmd <= 1'd1;
                end
                3'd5: begin
                end
@@ -11538,15 +11550,18 @@ end
 reg dummy_d_270;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_bankmachine7_cmd_payload_is_read <= 1'd0;
+       soc_litedramcore_bankmachine7_row_close <= 1'd0;
        case (vns_bankmachine7_state)
                1'd1: begin
+                       soc_litedramcore_bankmachine7_row_close <= 1'd1;
                end
                2'd2: begin
+                       soc_litedramcore_bankmachine7_row_close <= 1'd1;
                end
                2'd3: begin
                end
                3'd4: begin
+                       soc_litedramcore_bankmachine7_row_close <= 1'd1;
                end
                3'd5: begin
                end
@@ -11557,21 +11572,6 @@ always @(*) begin
                4'd8: begin
                end
                default: begin
-                       if (soc_litedramcore_bankmachine7_refresh_req) begin
-                       end else begin
-                               if (soc_litedramcore_bankmachine7_cmd_buffer_source_valid) begin
-                                       if (soc_litedramcore_bankmachine7_row_opened) begin
-                                               if (soc_litedramcore_bankmachine7_row_hit) begin
-                                                       if (soc_litedramcore_bankmachine7_cmd_buffer_source_payload_we) begin
-                                                       end else begin
-                                                               soc_litedramcore_bankmachine7_cmd_payload_is_read <= 1'd1;
-                                                       end
-                                               end else begin
-                                               end
-                                       end else begin
-                                       end
-                               end
-                       end
                end
        endcase
 // synthesis translate_off
@@ -11946,12 +11946,13 @@ end
 reg dummy_d_288;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_steerer_sel2 <= 2'd0;
+       soc_litedramcore_steerer_sel0 <= 2'd0;
        case (vns_multiplexer_state)
                1'd1: begin
-                       soc_litedramcore_steerer_sel2 <= 1'd1;
+                       soc_litedramcore_steerer_sel0 <= 1'd0;
                end
                2'd2: begin
+                       soc_litedramcore_steerer_sel0 <= 2'd3;
                end
                2'd3: begin
                end
@@ -11970,7 +11971,7 @@ always @(*) begin
                4'd10: begin
                end
                default: begin
-                       soc_litedramcore_steerer_sel2 <= 2'd2;
+                       soc_litedramcore_steerer_sel0 <= 1'd0;
                end
        endcase
 // synthesis translate_off
@@ -11982,13 +11983,10 @@ end
 reg dummy_d_289;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_choose_cmd_want_activates <= 1'd0;
+       soc_litedramcore_en1 <= 1'd0;
        case (vns_multiplexer_state)
                1'd1: begin
-                       if (1'd0) begin
-                       end else begin
-                               soc_litedramcore_choose_cmd_want_activates <= soc_litedramcore_ras_allowed;
-                       end
+                       soc_litedramcore_en1 <= 1'd1;
                end
                2'd2: begin
                end
@@ -12009,10 +12007,6 @@ always @(*) begin
                4'd10: begin
                end
                default: begin
-                       if (1'd0) begin
-                       end else begin
-                               soc_litedramcore_choose_cmd_want_activates <= soc_litedramcore_ras_allowed;
-                       end
                end
        endcase
 // synthesis translate_off
@@ -12024,10 +12018,10 @@ end
 reg dummy_d_290;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_steerer_sel3 <= 2'd0;
+       soc_litedramcore_steerer_sel1 <= 2'd0;
        case (vns_multiplexer_state)
                1'd1: begin
-                       soc_litedramcore_steerer_sel3 <= 2'd2;
+                       soc_litedramcore_steerer_sel1 <= 1'd1;
                end
                2'd2: begin
                end
@@ -12048,7 +12042,7 @@ always @(*) begin
                4'd10: begin
                end
                default: begin
-                       soc_litedramcore_steerer_sel3 <= 1'd0;
+                       soc_litedramcore_steerer_sel1 <= 1'd1;
                end
        endcase
 // synthesis translate_off
@@ -12060,9 +12054,10 @@ end
 reg dummy_d_291;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_en0 <= 1'd0;
+       soc_litedramcore_steerer_sel2 <= 2'd0;
        case (vns_multiplexer_state)
                1'd1: begin
+                       soc_litedramcore_steerer_sel2 <= 2'd2;
                end
                2'd2: begin
                end
@@ -12083,7 +12078,7 @@ always @(*) begin
                4'd10: begin
                end
                default: begin
-                       soc_litedramcore_en0 <= 1'd1;
+                       soc_litedramcore_steerer_sel2 <= 2'd2;
                end
        endcase
 // synthesis translate_off
@@ -12095,12 +12090,15 @@ end
 reg dummy_d_292;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_cmd_ready <= 1'd0;
+       soc_litedramcore_choose_cmd_want_activates <= 1'd0;
        case (vns_multiplexer_state)
                1'd1: begin
+                       if (1'd0) begin
+                       end else begin
+                               soc_litedramcore_choose_cmd_want_activates <= soc_litedramcore_ras_allowed;
+                       end
                end
                2'd2: begin
-                       soc_litedramcore_cmd_ready <= 1'd1;
                end
                2'd3: begin
                end
@@ -12119,6 +12117,10 @@ always @(*) begin
                4'd10: begin
                end
                default: begin
+                       if (1'd0) begin
+                       end else begin
+                               soc_litedramcore_choose_cmd_want_activates <= soc_litedramcore_ras_allowed;
+                       end
                end
        endcase
 // synthesis translate_off
@@ -12130,13 +12132,10 @@ end
 reg dummy_d_293;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_choose_cmd_cmd_ready <= 1'd0;
+       soc_litedramcore_steerer_sel3 <= 2'd0;
        case (vns_multiplexer_state)
                1'd1: begin
-                       if (1'd0) begin
-                       end else begin
-                               soc_litedramcore_choose_cmd_cmd_ready <= ((~((soc_litedramcore_choose_cmd_cmd_payload_ras & (~soc_litedramcore_choose_cmd_cmd_payload_cas)) & (~soc_litedramcore_choose_cmd_cmd_payload_we))) | soc_litedramcore_ras_allowed);
-                       end
+                       soc_litedramcore_steerer_sel3 <= 1'd0;
                end
                2'd2: begin
                end
@@ -12157,10 +12156,7 @@ always @(*) begin
                4'd10: begin
                end
                default: begin
-                       if (1'd0) begin
-                       end else begin
-                               soc_litedramcore_choose_cmd_cmd_ready <= ((~((soc_litedramcore_choose_cmd_cmd_payload_ras & (~soc_litedramcore_choose_cmd_cmd_payload_cas)) & (~soc_litedramcore_choose_cmd_cmd_payload_we))) | soc_litedramcore_ras_allowed);
-                       end
+                       soc_litedramcore_steerer_sel3 <= 1'd0;
                end
        endcase
 // synthesis translate_off
@@ -12172,7 +12168,7 @@ end
 reg dummy_d_294;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_choose_req_want_reads <= 1'd0;
+       soc_litedramcore_en0 <= 1'd0;
        case (vns_multiplexer_state)
                1'd1: begin
                end
@@ -12195,7 +12191,7 @@ always @(*) begin
                4'd10: begin
                end
                default: begin
-                       soc_litedramcore_choose_req_want_reads <= 1'd1;
+                       soc_litedramcore_en0 <= 1'd1;
                end
        endcase
 // synthesis translate_off
@@ -12207,12 +12203,12 @@ end
 reg dummy_d_295;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_choose_req_want_writes <= 1'd0;
+       soc_litedramcore_cmd_ready <= 1'd0;
        case (vns_multiplexer_state)
                1'd1: begin
-                       soc_litedramcore_choose_req_want_writes <= 1'd1;
                end
                2'd2: begin
+                       soc_litedramcore_cmd_ready <= 1'd1;
                end
                2'd3: begin
                end
@@ -12242,13 +12238,12 @@ end
 reg dummy_d_296;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_choose_req_cmd_ready <= 1'd0;
+       soc_litedramcore_choose_cmd_cmd_ready <= 1'd0;
        case (vns_multiplexer_state)
                1'd1: begin
                        if (1'd0) begin
-                               soc_litedramcore_choose_req_cmd_ready <= (soc_litedramcore_cas_allowed & ((~((soc_litedramcore_choose_req_cmd_payload_ras & (~soc_litedramcore_choose_req_cmd_payload_cas)) & (~soc_litedramcore_choose_req_cmd_payload_we))) | soc_litedramcore_ras_allowed));
                        end else begin
-                               soc_litedramcore_choose_req_cmd_ready <= soc_litedramcore_cas_allowed;
+                               soc_litedramcore_choose_cmd_cmd_ready <= ((~((soc_litedramcore_choose_cmd_cmd_payload_ras & (~soc_litedramcore_choose_cmd_cmd_payload_cas)) & (~soc_litedramcore_choose_cmd_cmd_payload_we))) | soc_litedramcore_ras_allowed);
                        end
                end
                2'd2: begin
@@ -12271,9 +12266,8 @@ always @(*) begin
                end
                default: begin
                        if (1'd0) begin
-                               soc_litedramcore_choose_req_cmd_ready <= (soc_litedramcore_cas_allowed & ((~((soc_litedramcore_choose_req_cmd_payload_ras & (~soc_litedramcore_choose_req_cmd_payload_cas)) & (~soc_litedramcore_choose_req_cmd_payload_we))) | soc_litedramcore_ras_allowed));
                        end else begin
-                               soc_litedramcore_choose_req_cmd_ready <= soc_litedramcore_cas_allowed;
+                               soc_litedramcore_choose_cmd_cmd_ready <= ((~((soc_litedramcore_choose_cmd_cmd_payload_ras & (~soc_litedramcore_choose_cmd_cmd_payload_cas)) & (~soc_litedramcore_choose_cmd_cmd_payload_we))) | soc_litedramcore_ras_allowed);
                        end
                end
        endcase
@@ -12286,10 +12280,9 @@ end
 reg dummy_d_297;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_en1 <= 1'd0;
+       soc_litedramcore_choose_req_want_reads <= 1'd0;
        case (vns_multiplexer_state)
                1'd1: begin
-                       soc_litedramcore_en1 <= 1'd1;
                end
                2'd2: begin
                end
@@ -12310,6 +12303,7 @@ always @(*) begin
                4'd10: begin
                end
                default: begin
+                       soc_litedramcore_choose_req_want_reads <= 1'd1;
                end
        endcase
 // synthesis translate_off
@@ -12321,13 +12315,12 @@ end
 reg dummy_d_298;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_steerer_sel0 <= 2'd0;
+       soc_litedramcore_choose_req_want_writes <= 1'd0;
        case (vns_multiplexer_state)
                1'd1: begin
-                       soc_litedramcore_steerer_sel0 <= 1'd0;
+                       soc_litedramcore_choose_req_want_writes <= 1'd1;
                end
                2'd2: begin
-                       soc_litedramcore_steerer_sel0 <= 2'd3;
                end
                2'd3: begin
                end
@@ -12346,7 +12339,6 @@ always @(*) begin
                4'd10: begin
                end
                default: begin
-                       soc_litedramcore_steerer_sel0 <= 1'd0;
                end
        endcase
 // synthesis translate_off
@@ -12358,10 +12350,14 @@ end
 reg dummy_d_299;
 // synthesis translate_on
 always @(*) begin
-       soc_litedramcore_steerer_sel1 <= 2'd0;
+       soc_litedramcore_choose_req_cmd_ready <= 1'd0;
        case (vns_multiplexer_state)
                1'd1: begin
-                       soc_litedramcore_steerer_sel1 <= 1'd0;
+                       if (1'd0) begin
+                               soc_litedramcore_choose_req_cmd_ready <= (soc_litedramcore_cas_allowed & ((~((soc_litedramcore_choose_req_cmd_payload_ras & (~soc_litedramcore_choose_req_cmd_payload_cas)) & (~soc_litedramcore_choose_req_cmd_payload_we))) | soc_litedramcore_ras_allowed));
+                       end else begin
+                               soc_litedramcore_choose_req_cmd_ready <= soc_litedramcore_cas_allowed;
+                       end
                end
                2'd2: begin
                end
@@ -12382,7 +12378,11 @@ always @(*) begin
                4'd10: begin
                end
                default: begin
-                       soc_litedramcore_steerer_sel1 <= 1'd1;
+                       if (1'd0) begin
+                               soc_litedramcore_choose_req_cmd_ready <= (soc_litedramcore_cas_allowed & ((~((soc_litedramcore_choose_req_cmd_payload_ras & (~soc_litedramcore_choose_req_cmd_payload_cas)) & (~soc_litedramcore_choose_req_cmd_payload_we))) | soc_litedramcore_ras_allowed));
+                       end else begin
+                               soc_litedramcore_choose_req_cmd_ready <= soc_litedramcore_cas_allowed;
+                       end
                end
        endcase
 // synthesis translate_off

diff --git a/microwatt.core b/microwatt.core
index 8bb510344308272a917b8a82219691d4863c60e8..a2d37df5804e14a9302175ac388cfb0e287f7afa 100644 (file)
--- a/microwatt.core
+++ b/microwatt.core
@@ -91,6 +91,12 @@ filesets:
       - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
       - fpga/top-acorn-cle-215.vhdl : {file_type : vhdlSource-2008}
 
+  genesys2:
+    files:
+      - fpga/genesys2.xdc : {file_type : xdc}
+      - fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
+      - fpga/top-genesys2.vhdl : {file_type : vhdlSource-2008}
+
   arty_a7:
     files:
       - fpga/arty_a7.xdc : {file_type : xdc}
@@ -144,6 +150,23 @@ targets:
       vivado: {part : xc7a200tsbg484-2}
     toplevel : toplevel
 
+  genesys2-nodram:
+    default_tool: vivado
+    filesets: [core, genesys2, soc, fpga, debug_xilinx, uart16550, xilinx_specific]
+    parameters :
+      - memory_size
+      - ram_init_file
+      - clk_frequency
+      - use_litedram=false
+      - no_bram=false
+      - disable_flatten_core
+      - spi_flash_offset=10485760
+      - log_length=2048
+      - uart_is_16550=false
+    tools:
+      vivado: {part : xc7k325tffg900-2}
+    toplevel : toplevel
+
   acorn-cle-215:
     default_tool: vivado
     filesets: [core, acorn_cle_215, soc, fpga, debug_xilinx, litedram, uart16550, xilinx_specific]
@@ -161,6 +184,23 @@ targets:
       vivado: {part : xc7a200tsbg484-2}
     toplevel : toplevel
 
+  genesys2:
+    default_tool: vivado
+    filesets: [core, genesys2, soc, fpga, debug_xilinx, litedram, uart16550, xilinx_specific]
+    parameters :
+      - memory_size
+      - ram_init_file
+      - use_litedram=true
+      - disable_flatten_core
+      - no_bram
+      - spi_flash_offset=10485760
+      - log_length=2048
+      - uart_is_16550=false
+    generate: [litedram_genesys2]
+    tools:
+      vivado: {part : xc7k325tffg900-2}
+    toplevel : toplevel
+
   nexys_video-nodram:
     default_tool: vivado
     filesets: [core, nexys_video, soc, fpga, debug_xilinx, uart16550, xilinx_specific]
@@ -305,6 +345,10 @@ generate:
     generator: litedram_gen
     parameters: {board : acorn-cle-215}
 
+  litedram_genesys2:
+    generator: litedram_gen
+    parameters: {board : genesys2}
+
 parameters:
   memory_size:
     datatype    : int