another attempt at fixing clock routing issues

diff --git a/build.py b/build.py
index a87c8a3073d0a511723c99db96f3ee90919ee498..73bd7720b6c6049922203a5eb3b2233882bf460c 100755 (executable)
--- a/build.py
+++ b/build.py
@@ -18,8 +18,6 @@ TIMESPEC "TSclk50" = PERIOD "GRPclk50" 20 ns HIGH 50%;
 """, clk50=platform.lookup_request("clk50"))
 
        platform.add_platform_command("""
-INST "m1crg/pll" LOC="PLL_ADV_X0Y1";
-INST "m1crg/vga_clock_gen" LOC="DCM_X0Y6";
 INST "m1crg/wr_bufpll" LOC = "BUFPLL_X0Y2";
 INST "m1crg/rd_bufpll" LOC = "BUFPLL_X0Y3";
 

diff --git a/verilog/m1crg/m1crg.v b/verilog/m1crg/m1crg.v
index 596b00d4c0b6ad3c239de271ec9099ff6ca7306a..10e30e040949e5c23259b3f3a9d77cefdc876f8c 100644 (file)
--- a/verilog/m1crg/m1crg.v
+++ b/verilog/m1crg/m1crg.v
@@ -209,6 +209,12 @@ BUFG bufg_x1(
        .O(sys_clk)
 );
 
+wire clk50g;
+BUFG bufg_50(
+       .I(pllout4),
+       .O(clk50g)
+);
+
 wire clk2x_off;
 BUFG bufg_x2_offclk(
        .I(pllout5),
@@ -253,7 +259,7 @@ ODDR2 #(
  * Ethernet PHY 
  */
 
-always @(posedge pllout4)
+always @(posedge clk50g)
        eth_phy_clk_pad <= ~eth_phy_clk_pad;
 
 /* Let the synthesizer insert the appropriate buffers */
@@ -277,7 +283,7 @@ DCM_CLKGEN #(
        .CLKFX180(),
        .CLKFXDV(),
        .STATUS(),
-       .CLKIN(pllout4),
+       .CLKIN(clk50g),
        .FREEZEDCM(1'b0),
        .PROGCLK(vga_progclk),
        .PROGDATA(vga_progdata),