intel: Map M9K BRAM only on families that have it

This regresses Cyclone V and Cyclone 10 substantially, but these
numbers were artificial, targeting a BRAM that they did not contain.

Amusingly, synth_intel still does better when synthesizing PicoSoC
than Quartus when neither are inferring block RAM.

diff --git a/techlibs/intel/Makefile.inc b/techlibs/intel/Makefile.inc
index ec7cea379a262b06e959aa51dccaf8154fb9252d..7a3d2c71a79246a42362a3ed22e0544084fc66dc 100644 (file)
--- a/techlibs/intel/Makefile.inc
+++ b/techlibs/intel/Makefile.inc
@@ -3,8 +3,8 @@ OBJS += techlibs/intel/synth_intel.o
 
 $(eval $(call add_share_file,share/intel/common,techlibs/intel/common/m9k_bb.v))
 $(eval $(call add_share_file,share/intel/common,techlibs/intel/common/altpll_bb.v))
-$(eval $(call add_share_file,share/intel/common,techlibs/intel/common/brams.txt))
-$(eval $(call add_share_file,share/intel/common,techlibs/intel/common/brams_map.v))
+$(eval $(call add_share_file,share/intel/common,techlibs/intel/common/brams_m9k.txt))
+$(eval $(call add_share_file,share/intel/common,techlibs/intel/common/brams_map_m9k.v))
 $(eval $(call add_share_file,share/intel/max10,techlibs/intel/max10/cells_sim.v))
 $(eval $(call add_share_file,share/intel/a10gx,techlibs/intel/a10gx/cells_sim.v))
 $(eval $(call add_share_file,share/intel/cyclonev,techlibs/intel/cyclonev/cells_sim.v))

diff --git a/techlibs/intel/common/brams.txt b/techlibs/intel/common/brams.txt
deleted file mode 100644 (file)
index 3bf21af..0000000
--- a/techlibs/intel/common/brams.txt
+++ /dev/null
@@ -1,33 +0,0 @@
-bram $__M9K_ALTSYNCRAM_SINGLEPORT_FULL
-  init   1
-  abits  13 @M1
-  dbits  1  @M1
-  abits  12 @M2
-  dbits  2  @M2
-  abits  11 @M3
-  dbits  4  @M3
-  abits  10 @M4
-  dbits  8  @M4
-  abits  10 @M5
-  dbits  9  @M5
-  abits  9  @M6
-  dbits  16 @M6
-  abits  9  @M7
-  dbits  18 @M7
-  abits  8  @M8
-  dbits  32 @M8
-  abits  8  @M9
-  dbits  36 @M9
-  groups 2
-  ports  1 1
-  wrmode 0 1
-  enable 1 1
-  transp 0 0
-  clocks 2 3
-  clkpol 2 3
-endbram
-
-match $__M9K_ALTSYNCRAM_SINGLEPORT_FULL
-  min efficiency 2
-  make_transp
-endmatch

diff --git a/techlibs/intel/common/brams_m9k.txt b/techlibs/intel/common/brams_m9k.txt
new file mode 100644 (file)
index 0000000..3bf21af
--- /dev/null
+++ b/techlibs/intel/common/brams_m9k.txt
@@ -0,0 +1,33 @@
+bram $__M9K_ALTSYNCRAM_SINGLEPORT_FULL
+  init   1
+  abits  13 @M1
+  dbits  1  @M1
+  abits  12 @M2
+  dbits  2  @M2
+  abits  11 @M3
+  dbits  4  @M3
+  abits  10 @M4
+  dbits  8  @M4
+  abits  10 @M5
+  dbits  9  @M5
+  abits  9  @M6
+  dbits  16 @M6
+  abits  9  @M7
+  dbits  18 @M7
+  abits  8  @M8
+  dbits  32 @M8
+  abits  8  @M9
+  dbits  36 @M9
+  groups 2
+  ports  1 1
+  wrmode 0 1
+  enable 1 1
+  transp 0 0
+  clocks 2 3
+  clkpol 2 3
+endbram
+
+match $__M9K_ALTSYNCRAM_SINGLEPORT_FULL
+  min efficiency 2
+  make_transp
+endmatch

diff --git a/techlibs/intel/common/brams_map.v b/techlibs/intel/common/brams_map.v
deleted file mode 100644 (file)
index d0f07c1..0000000
--- a/techlibs/intel/common/brams_map.v
+++ /dev/null
@@ -1,93 +0,0 @@
-module \$__M9K_ALTSYNCRAM_SINGLEPORT_FULL (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
-
-   parameter CFG_ABITS = 8;
-   parameter CFG_DBITS = 36;
-   parameter ABITS = 1;
-   parameter DBITS = 1;
-   parameter CLKPOL2 = 1;
-   parameter CLKPOL3 = 1;
-
-   input CLK2;
-   input CLK3;
-   //Read data
-   output [CFG_DBITS-1:0] A1DATA;
-   input [CFG_ABITS-1:0]  A1ADDR;
-   input                  A1EN;
-   //Write data
-   output [CFG_DBITS-1:0] B1DATA;
-   input [CFG_ABITS-1:0]  B1ADDR;
-   input                  B1EN;
-
-   wire [CFG_DBITS-1:0]   B1DATA_t;
-
-   localparam MODE = CFG_DBITS == 1  ? 1:
-                     CFG_DBITS == 2  ? 2:
-                     CFG_DBITS == 4  ? 3:
-                     CFG_DBITS == 8  ? 4:
-                     CFG_DBITS == 9  ? 5:
-                     CFG_DBITS == 16 ? 6:
-                     CFG_DBITS == 18 ? 7:
-                     CFG_DBITS == 32 ? 8:
-                     CFG_DBITS == 36 ? 9:
-                     'bx;
-
-   localparam NUMWORDS = CFG_DBITS == 1  ? 8192:
-                         CFG_DBITS == 2  ? 4096:
-                         CFG_DBITS == 4  ? 2048:
-                         CFG_DBITS == 8  ? 1024:
-                         CFG_DBITS == 9  ? 1024:
-                         CFG_DBITS == 16 ?  512:
-                         CFG_DBITS == 18 ?  512:
-                         CFG_DBITS == 32 ?  256:
-                         CFG_DBITS == 36 ?  256:
-                         'bx;
-
-   altsyncram  #(.clock_enable_input_b           ("ALTERNATE"   ),
-                 .clock_enable_input_a           ("ALTERNATE"   ),
-                 .clock_enable_output_b          ("NORMAL"      ),
-                 .clock_enable_output_a          ("NORMAL"      ),
-                 .wrcontrol_aclr_a               ("NONE"        ),
-                 .indata_aclr_a                  ("NONE"        ),
-                 .address_aclr_a                 ("NONE"        ),
-                 .outdata_aclr_a                 ("NONE"        ),
-                 .outdata_reg_a                  ("UNREGISTERED"),
-                 .operation_mode                 ("SINGLE_PORT" ),
-                 .intended_device_family         ("CYCLONE IVE" ),
-                 .outdata_reg_a                  ("UNREGISTERED"),
-                 .lpm_type                       ("altsyncram"  ),
-                 .init_type                      ("unused"      ),
-                 .ram_block_type                 ("AUTO"        ),
-                 .lpm_hint                       ("ENABLE_RUNTIME_MOD=NO"), // Forced value
-                 .power_up_uninitialized         ("FALSE"),
-                 .read_during_write_mode_port_a  ("NEW_DATA_NO_NBE_READ"), // Forced value
-                 .width_byteena_a                (1), // Forced value
-                 .numwords_b                     ( NUMWORDS     ),
-                 .numwords_a                     ( NUMWORDS     ),
-                 .widthad_b                      ( CFG_DBITS    ),
-                 .width_b                        ( CFG_ABITS    ),
-                 .widthad_a                      ( CFG_DBITS    ),
-                 .width_a                        ( CFG_ABITS    )
-                 ) _TECHMAP_REPLACE_ (
-                                      .data_a(B1DATA),
-                                      .address_a(B1ADDR),
-                                      .wren_a(B1EN),
-                                      .rden_a(A1EN),
-                                      .q_a(A1DATA),
-                                      .data_b(B1DATA),
-                                      .address_b(0),
-                                      .wren_b(1'b0),
-                                      .rden_b(1'b0),
-                                      .q_b(),
-                                      .clock0(CLK2),
-                                      .clock1(1'b1), // Unused in single port mode
-                                      .clocken0(1'b1),
-                                      .clocken1(1'b1),
-                                      .clocken2(1'b1),
-                                      .clocken3(1'b1),
-                                      .aclr0(1'b0),
-                                      .aclr1(1'b0),
-                                      .addressstall_a(1'b0),
-                                      .addressstall_b(1'b0));
-
-endmodule
-

diff --git a/techlibs/intel/common/brams_map_m9k.v b/techlibs/intel/common/brams_map_m9k.v
new file mode 100644 (file)
index 0000000..d0f07c1
--- /dev/null
+++ b/techlibs/intel/common/brams_map_m9k.v
@@ -0,0 +1,93 @@
+module \$__M9K_ALTSYNCRAM_SINGLEPORT_FULL (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
+
+   parameter CFG_ABITS = 8;
+   parameter CFG_DBITS = 36;
+   parameter ABITS = 1;
+   parameter DBITS = 1;
+   parameter CLKPOL2 = 1;
+   parameter CLKPOL3 = 1;
+
+   input CLK2;
+   input CLK3;
+   //Read data
+   output [CFG_DBITS-1:0] A1DATA;
+   input [CFG_ABITS-1:0]  A1ADDR;
+   input                  A1EN;
+   //Write data
+   output [CFG_DBITS-1:0] B1DATA;
+   input [CFG_ABITS-1:0]  B1ADDR;
+   input                  B1EN;
+
+   wire [CFG_DBITS-1:0]   B1DATA_t;
+
+   localparam MODE = CFG_DBITS == 1  ? 1:
+                     CFG_DBITS == 2  ? 2:
+                     CFG_DBITS == 4  ? 3:
+                     CFG_DBITS == 8  ? 4:
+                     CFG_DBITS == 9  ? 5:
+                     CFG_DBITS == 16 ? 6:
+                     CFG_DBITS == 18 ? 7:
+                     CFG_DBITS == 32 ? 8:
+                     CFG_DBITS == 36 ? 9:
+                     'bx;
+
+   localparam NUMWORDS = CFG_DBITS == 1  ? 8192:
+                         CFG_DBITS == 2  ? 4096:
+                         CFG_DBITS == 4  ? 2048:
+                         CFG_DBITS == 8  ? 1024:
+                         CFG_DBITS == 9  ? 1024:
+                         CFG_DBITS == 16 ?  512:
+                         CFG_DBITS == 18 ?  512:
+                         CFG_DBITS == 32 ?  256:
+                         CFG_DBITS == 36 ?  256:
+                         'bx;
+
+   altsyncram  #(.clock_enable_input_b           ("ALTERNATE"   ),
+                 .clock_enable_input_a           ("ALTERNATE"   ),
+                 .clock_enable_output_b          ("NORMAL"      ),
+                 .clock_enable_output_a          ("NORMAL"      ),
+                 .wrcontrol_aclr_a               ("NONE"        ),
+                 .indata_aclr_a                  ("NONE"        ),
+                 .address_aclr_a                 ("NONE"        ),
+                 .outdata_aclr_a                 ("NONE"        ),
+                 .outdata_reg_a                  ("UNREGISTERED"),
+                 .operation_mode                 ("SINGLE_PORT" ),
+                 .intended_device_family         ("CYCLONE IVE" ),
+                 .outdata_reg_a                  ("UNREGISTERED"),
+                 .lpm_type                       ("altsyncram"  ),
+                 .init_type                      ("unused"      ),
+                 .ram_block_type                 ("AUTO"        ),
+                 .lpm_hint                       ("ENABLE_RUNTIME_MOD=NO"), // Forced value
+                 .power_up_uninitialized         ("FALSE"),
+                 .read_during_write_mode_port_a  ("NEW_DATA_NO_NBE_READ"), // Forced value
+                 .width_byteena_a                (1), // Forced value
+                 .numwords_b                     ( NUMWORDS     ),
+                 .numwords_a                     ( NUMWORDS     ),
+                 .widthad_b                      ( CFG_DBITS    ),
+                 .width_b                        ( CFG_ABITS    ),
+                 .widthad_a                      ( CFG_DBITS    ),
+                 .width_a                        ( CFG_ABITS    )
+                 ) _TECHMAP_REPLACE_ (
+                                      .data_a(B1DATA),
+                                      .address_a(B1ADDR),
+                                      .wren_a(B1EN),
+                                      .rden_a(A1EN),
+                                      .q_a(A1DATA),
+                                      .data_b(B1DATA),
+                                      .address_b(0),
+                                      .wren_b(1'b0),
+                                      .rden_b(1'b0),
+                                      .q_b(),
+                                      .clock0(CLK2),
+                                      .clock1(1'b1), // Unused in single port mode
+                                      .clocken0(1'b1),
+                                      .clocken1(1'b1),
+                                      .clocken2(1'b1),
+                                      .clocken3(1'b1),
+                                      .aclr0(1'b0),
+                                      .aclr1(1'b0),
+                                      .addressstall_a(1'b0),
+                                      .addressstall_b(1'b0));
+
+endmodule
+

diff --git a/techlibs/intel/synth_intel.cc b/techlibs/intel/synth_intel.cc
index d7b0895030cf649f66efaffb1c827c9167779438..87d83f0db1325f825cce2880ea47b82c66b22614 100644 (file)
--- a/techlibs/intel/synth_intel.cc
+++ b/techlibs/intel/synth_intel.cc
@@ -187,8 +187,15 @@ struct SynthIntelPass : public ScriptPass {
                }
 
                if (!nobram && check_label("map_bram", "(skip if -nobram)")) {
-                       run("memory_bram -rules +/intel/common/brams.txt");
-                       run("techmap -map +/intel/common/brams_map.v");
+                        if (family_opt == "cycloneiv" ||
+                            family_opt == "cycloneive" ||
+                            family_opt == "max10" ||
+                            help_mode) {
+                               run("memory_bram -rules +/intel/common/brams_m9k.txt", "(if applicable for family)");
+                               run("techmap -map +/intel/common/brams_map_m9k.v", "(if applicable for family)");
+                       } else {
+                               log_warning("BRAM mapping is not currently supported for %s.\n", family_opt.c_str());
+                       }
                }
 
                if (check_label("map_ffram")) {
@@ -217,7 +224,7 @@ struct SynthIntelPass : public ScriptPass {
                if (check_label("map_cells")) {
                        if (!noiopads)
                                run("iopadmap -bits -outpad $__outpad I:O -inpad $__inpad O:I", "(unless -noiopads)");
-                        run(stringf("techmap -map +/intel/%s/cells_map.v", family_opt.c_str()));
+                       run(stringf("techmap -map +/intel/%s/cells_map.v", family_opt.c_str()));
 
                        run("dffinit -highlow -ff dffeas q power_up");
                        run("clean -purge");