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diff --git a/Harmonised_RVV/Packed_SIMD.mdwn b/Harmonised_RVV/Packed_SIMD.mdwn
index 75d7b3c8ccf36c31fd8595366fb4adebf3f23ac3..a9593b2d6fc61d944b08a37d14db82121be0c865 100644 (file)
--- a/Harmonised_RVV/Packed_SIMD.mdwn
+++ b/Harmonised_RVV/Packed_SIMD.mdwn
@@ -10,7 +10,7 @@ RVP implementations may choose to load/store to/from Integer register file (rath
 * Thus, RVP implementations have a choice of providing a dedicated Vector register file, or sharing the integer register file, but not both  simultaneously.  (Supporting both would need a CSR mode switch bit).
 * If integer register file is used for vector operations, any callee saved registers (r2-4, 8-9, 18-27) must be saved with RVI SW or SD instructions, before being used as vector registers (this register saving behaviour is harmless but redundant when RVP code is run on a machine with a dedicated vector reg file).
 
-##### VLDX, VSTX, VLDS, VSTS are not supported in RVP
+##### VLDX, VSTX, VLDS, VSTS are not supported in hardware
 To keep RVP implementations simple, these instructions will trap, and may be implemented as software emulation
 
 ##### Default register "banks" and types