Ruby: Correctly set access permissions for directory entries

The access permissions for the directory entries are not being set correctly.
This is because pointers are not used for handling directory entries.
function. get and set functions for access permissions have been added to the
Controller state machine. The changePermission() function provided by the
AbstractEntry and AbstractCacheEntry classes has been exposed to SLICC
code once again. The set_permission() functionality has been removed.

NOTE: Each protocol will have to define these get and set functions in order
to compile successfully.

diff --git a/src/mem/protocol/MESI_CMP_directory-L1cache.sm b/src/mem/protocol/MESI_CMP_directory-L1cache.sm
index d0fc61e90663aab7ee3a301b46810fdf24987e41..ebbd09ae09da80f87c5ed17adb73b1b88b06fd16 100644 (file)
--- a/src/mem/protocol/MESI_CMP_directory-L1cache.sm
+++ b/src/mem/protocol/MESI_CMP_directory-L1cache.sm
@@ -183,6 +183,26 @@ machine(L1Cache, "MSI Directory L1 Cache CMP")
     }
   }
 
+  AccessPermission getAccessPermission(Address addr) {
+    TBE tbe := L1_TBEs[addr];
+    if(is_valid(tbe)) {
+      return L1Cache_State_to_permission(tbe.TBEState);
+    }
+
+    Entry cache_entry := getCacheEntry(addr);
+    if(is_valid(cache_entry)) {
+      return L1Cache_State_to_permission(cache_entry.CacheState);
+    }
+
+    return AccessPermission:NotPresent;
+  }
+
+  void setAccessPermission(Entry cache_entry, Address addr, State state) {
+    if (is_valid(cache_entry)) {
+      cache_entry.changePermission(L1Cache_State_to_permission(state));
+    }
+  }
+
   Event mandatory_request_type_to_event(RubyRequestType type) {
     if (type == RubyRequestType:LD) {
       return Event:Load;

diff --git a/src/mem/protocol/MESI_CMP_directory-L2cache.sm b/src/mem/protocol/MESI_CMP_directory-L2cache.sm
index 771a2dfb230c7a33dd43d10c4a2a8847638d36ab..6044f5233c00a5bbfa48534cf74b527fcd34607f 100644 (file)
--- a/src/mem/protocol/MESI_CMP_directory-L2cache.sm
+++ b/src/mem/protocol/MESI_CMP_directory-L2cache.sm
@@ -202,7 +202,6 @@ machine(L2Cache, "MESI Directory L2 Cache CMP")
     return L2Cache_State_to_string(getState(tbe, cache_entry, addr));
   }
 
-  // when is this called
   void setState(TBE tbe, Entry cache_entry, Address addr, State state) {
 
     // MUST CHANGE
@@ -215,6 +214,26 @@ machine(L2Cache, "MESI Directory L2 Cache CMP")
     }
   }
 
+  AccessPermission getAccessPermission(Address addr) {
+    TBE tbe := L2_TBEs[addr];
+    if(is_valid(tbe)) {
+      return L2Cache_State_to_permission(tbe.TBEState);
+    }
+
+    Entry cache_entry := getCacheEntry(addr);
+    if(is_valid(cache_entry)) {
+      return L2Cache_State_to_permission(cache_entry.CacheState);
+    }
+
+    return AccessPermission:NotPresent;
+  }
+
+  void setAccessPermission(Entry cache_entry, Address addr, State state) {
+    if (is_valid(cache_entry)) {
+      cache_entry.changePermission(L2Cache_State_to_permission(state));
+    }
+  }
+
   Event L1Cache_request_type_to_event(CoherenceRequestType type, Address addr,
                                       MachineID requestor, Entry cache_entry) {
     if(type == CoherenceRequestType:GETS) {

diff --git a/src/mem/protocol/MESI_CMP_directory-dir.sm b/src/mem/protocol/MESI_CMP_directory-dir.sm
index 6ad88f8091bfaa3ecd58c26c9040380e51ef87c4..6e3e796417ea5538ce14f337c40de86ce17de2b4 100644 (file)
--- a/src/mem/protocol/MESI_CMP_directory-dir.sm
+++ b/src/mem/protocol/MESI_CMP_directory-dir.sm
@@ -124,7 +124,6 @@ machine(Directory, "MESI_CMP_filter_directory protocol")
     }
   }  
    
-
   void setState(TBE tbe, Address addr, State state) {
 
     if (is_valid(tbe)) {
@@ -145,6 +144,20 @@ machine(Directory, "MESI_CMP_filter_directory protocol")
     }
   }
 
+  AccessPermission getAccessPermission(Address addr) {
+    TBE tbe := TBEs[addr];
+    if(is_valid(tbe)) {
+      return Directory_State_to_permission(tbe.TBEState);
+    }
+
+    return Directory_State_to_permission(getDirectoryEntry(addr).DirectoryState);
+  }
+
+  void setAccessPermission(Address addr, State state) {
+    if (directory.isPresent(addr)) {
+      getDirectoryEntry(addr).changePermission(Directory_State_to_permission(state));
+    }
+  }
 
   bool isGETRequest(CoherenceRequestType type) {
     return (type == CoherenceRequestType:GETS) ||

diff --git a/src/mem/protocol/MESI_CMP_directory-dma.sm b/src/mem/protocol/MESI_CMP_directory-dma.sm
index 205d337b1664b2a265400f8e91ff351621bb361f..aee2e467d3f294958d6b2dd1197e074e2b08a63e 100644 (file)
--- a/src/mem/protocol/MESI_CMP_directory-dma.sm
+++ b/src/mem/protocol/MESI_CMP_directory-dma.sm
@@ -35,6 +35,13 @@ machine(DMA, "DMA Controller")
   cur_state := state;
   }
 
+  AccessPermission getAccessPermission(Address addr) {
+    return AccessPermission:NotPresent;
+  }
+
+  void setAccessPermission(Address addr, State state) {
+  }
+
   out_port(reqToDirectory_out, RequestMsg, reqToDirectory, desc="...");
 
   in_port(dmaRequestQueue_in, SequencerMsg, mandatoryQueue, desc="...") {

diff --git a/src/mem/protocol/MI_example-cache.sm b/src/mem/protocol/MI_example-cache.sm
index cef89afda1357f60f1d6992d43a3cf2c03c92688..afc415b5a335faa795af9997a1e30f05289f2d6d 100644 (file)
--- a/src/mem/protocol/MI_example-cache.sm
+++ b/src/mem/protocol/MI_example-cache.sm
@@ -120,6 +120,26 @@ machine(L1Cache, "MI Example L1 Cache")
     }
   }
 
+  AccessPermission getAccessPermission(Address addr) {
+    TBE tbe := TBEs[addr];
+    if(is_valid(tbe)) {
+      return L1Cache_State_to_permission(tbe.TBEState);
+    }
+
+    Entry cache_entry := getCacheEntry(addr);
+    if(is_valid(cache_entry)) {
+      return L1Cache_State_to_permission(cache_entry.CacheState);
+    }
+
+    return AccessPermission:NotPresent;
+  }
+
+  void setAccessPermission(Entry cache_entry, Address addr, State state) {
+    if (is_valid(cache_entry)) {
+      cache_entry.changePermission(L1Cache_State_to_permission(state));
+    }
+  }
+
   GenericMachineType getNondirectHitMachType(MachineID sender) {
     if (machineIDToMachineType(sender) == MachineType:L1Cache) {
       //

diff --git a/src/mem/protocol/MI_example-dir.sm b/src/mem/protocol/MI_example-dir.sm
index bffdd04fd3aefb6050f77dda3e58875d6f8416b6..baffe24120a060d02030af86ce6dff3b83bdebfb 100644 (file)
--- a/src/mem/protocol/MI_example-dir.sm
+++ b/src/mem/protocol/MI_example-dir.sm
@@ -116,6 +116,21 @@ machine(Directory, "Directory protocol")
     }
   }
 
+  AccessPermission getAccessPermission(Address addr) {
+    TBE tbe := TBEs[addr];
+    if(is_valid(tbe)) {
+      return Directory_State_to_permission(tbe.TBEState);
+    }
+
+    return Directory_State_to_permission(getDirectoryEntry(addr).DirectoryState);
+  }
+
+  void setAccessPermission(Address addr, State state) {
+    if (directory.isPresent(addr)) {
+      getDirectoryEntry(addr).changePermission(Directory_State_to_permission(state));
+    }
+  }
+
   // ** OUT_PORTS **
   out_port(forwardNetwork_out, RequestMsg, forwardFromDir);
   out_port(responseNetwork_out, ResponseMsg, responseFromDir);

diff --git a/src/mem/protocol/MI_example-dma.sm b/src/mem/protocol/MI_example-dma.sm
index bb864e934f2d2452421ccacc7ddab39736a2cf87..8d79976fc10e8352a12053baaaf9cd951510508c 100644 (file)
--- a/src/mem/protocol/MI_example-dma.sm
+++ b/src/mem/protocol/MI_example-dma.sm
@@ -30,6 +30,13 @@ machine(DMA, "DMA Controller")
   cur_state := state;
   }
 
+  AccessPermission getAccessPermission(Address addr) {
+    return AccessPermission:NotPresent;
+  }
+
+  void setAccessPermission(Address addr, State state) {
+  }
+
   out_port(reqToDirectory_out, DMARequestMsg, reqToDirectory, desc="...");
 
   in_port(dmaRequestQueue_in, SequencerMsg, mandatoryQueue, desc="...") {

diff --git a/src/mem/protocol/MOESI_CMP_directory-L1cache.sm b/src/mem/protocol/MOESI_CMP_directory-L1cache.sm
index e9622c30bdd830d2ed5948fef94459b93771cddd..35832ee9ca9cb419167f768fb3451150d11cf04d 100644 (file)
--- a/src/mem/protocol/MOESI_CMP_directory-L1cache.sm
+++ b/src/mem/protocol/MOESI_CMP_directory-L1cache.sm
@@ -194,6 +194,26 @@ machine(L1Cache, "Directory protocol")
     }
   }
 
+  AccessPermission getAccessPermission(Address addr) {
+    TBE tbe := TBEs[addr];
+    if(is_valid(tbe)) {
+      return L1Cache_State_to_permission(tbe.TBEState);
+    }
+
+    Entry cache_entry := getCacheEntry(addr);
+    if(is_valid(cache_entry)) {
+      return L1Cache_State_to_permission(cache_entry.CacheState);
+    }
+
+    return AccessPermission:NotPresent;
+  }
+
+  void setAccessPermission(Entry cache_entry, Address addr, State state) {
+    if (is_valid(cache_entry)) {
+      cache_entry.changePermission(L1Cache_State_to_permission(state));
+    }
+  }
+
   Event mandatory_request_type_to_event(RubyRequestType type) {
     if (type == RubyRequestType:LD) {
       return Event:Load;

diff --git a/src/mem/protocol/MOESI_CMP_directory-L2cache.sm b/src/mem/protocol/MOESI_CMP_directory-L2cache.sm
index a9c1e74a02c86d1b5fc46df0c2a506ae9ec621c3..8202a9c2f33c666cbd04ee53ee9e0f68fa410b9d 100644 (file)
--- a/src/mem/protocol/MOESI_CMP_directory-L2cache.sm
+++ b/src/mem/protocol/MOESI_CMP_directory-L2cache.sm
@@ -499,6 +499,26 @@ machine(L2Cache, "Token protocol")
     }
   }
 
+  AccessPermission getAccessPermission(Address addr) {
+    TBE tbe := TBEs[addr];
+    if(is_valid(tbe)) {
+      return L2Cache_State_to_permission(tbe.TBEState);
+    }
+
+    Entry cache_entry := getCacheEntry(addr);
+    if(is_valid(cache_entry)) {
+      return L2Cache_State_to_permission(cache_entry.CacheState);
+    }
+
+    return AccessPermission:NotPresent;
+  }
+
+  void setAccessPermission(Entry cache_entry, Address addr, State state) {
+    if (is_valid(cache_entry)) {
+      cache_entry.changePermission(L2Cache_State_to_permission(state));
+    }
+  }
+
   MessageBuffer triggerQueue, ordered="true";
 
   out_port(globalRequestNetwork_out, RequestMsg, GlobalRequestFromL2Cache);

diff --git a/src/mem/protocol/MOESI_CMP_directory-dir.sm b/src/mem/protocol/MOESI_CMP_directory-dir.sm
index 572101f002bd6cf82e4b99ea8a91f77d3aac652b..b13b56ffb3238337e7abc8ecae56cc6d3e872329 100644 (file)
--- a/src/mem/protocol/MOESI_CMP_directory-dir.sm
+++ b/src/mem/protocol/MOESI_CMP_directory-dir.sm
@@ -171,6 +171,20 @@ machine(Directory, "Directory protocol")
     }
   }
 
+  AccessPermission getAccessPermission(Address addr) {
+    if (directory.isPresent(addr)) {
+      return Directory_State_to_permission(getDirectoryEntry(addr).DirectoryState);
+    }
+
+    return AccessPermission:NotPresent;
+  }
+
+  void setAccessPermission(Address addr, State state) {
+    if (directory.isPresent(addr)) {
+      getDirectoryEntry(addr).changePermission(Directory_State_to_permission(state));
+    }
+  }
+
   // if no sharers, then directory can be considered both a sharer and exclusive w.r.t. coherence checking
   bool isBlockShared(Address addr) {
     if (directory.isPresent(addr)) {

diff --git a/src/mem/protocol/MOESI_CMP_directory-dma.sm b/src/mem/protocol/MOESI_CMP_directory-dma.sm
index 642c6e22d57ddf59d83867a92393c85571f6465e..0d99e354e415975b7580b15814af699ef16cce6d 100644 (file)
--- a/src/mem/protocol/MOESI_CMP_directory-dma.sm
+++ b/src/mem/protocol/MOESI_CMP_directory-dma.sm
@@ -61,6 +61,13 @@ machine(DMA, "DMA Controller")
   cur_state := state;
   }
 
+  AccessPermission getAccessPermission(Address addr) {
+    return AccessPermission:NotPresent;
+  }
+
+  void setAccessPermission(Address addr, State state) {
+  }
+
   out_port(reqToDirectory_out, RequestMsg, reqToDir, desc="...");
   out_port(respToDirectory_out, ResponseMsg, respToDir, desc="...");
   out_port(foo1_out, ResponseMsg, foo1, desc="...");

diff --git a/src/mem/protocol/MOESI_CMP_token-L1cache.sm b/src/mem/protocol/MOESI_CMP_token-L1cache.sm
index a4dbe5fe781c360c7d2f4add4ffde99e235c841c..d557132fc7bff3a1d80d8b69b61d6be526e00401 100644 (file)
--- a/src/mem/protocol/MOESI_CMP_token-L1cache.sm
+++ b/src/mem/protocol/MOESI_CMP_token-L1cache.sm
@@ -341,6 +341,26 @@ machine(L1Cache, "Token protocol")
     }
   }
 
+  AccessPermission getAccessPermission(Address addr) {
+    TBE tbe := L1_TBEs[addr];
+    if(is_valid(tbe)) {
+      return L1Cache_State_to_permission(tbe.TBEState);
+    }
+
+    Entry cache_entry := getCacheEntry(addr);
+    if(is_valid(cache_entry)) {
+      return L1Cache_State_to_permission(cache_entry.CacheState);
+    }
+
+    return AccessPermission:NotPresent;
+  }
+
+  void setAccessPermission(Entry cache_entry, Address addr, State state) {
+    if (is_valid(cache_entry)) {
+      cache_entry.changePermission(L1Cache_State_to_permission(state));
+    }
+  }
+
   Event mandatory_request_type_to_event(RubyRequestType type) {
     if (type == RubyRequestType:LD) {
       return Event:Load;

diff --git a/src/mem/protocol/MOESI_CMP_token-L2cache.sm b/src/mem/protocol/MOESI_CMP_token-L2cache.sm
index 8b87889b1e6dbd588899ab90e2b91188b3ac2ab3..c9c729263aed2b30f96cef9742fd01928463d302 100644 (file)
--- a/src/mem/protocol/MOESI_CMP_token-L2cache.sm
+++ b/src/mem/protocol/MOESI_CMP_token-L2cache.sm
@@ -211,6 +211,21 @@ machine(L2Cache, "Token protocol")
     }
   }
 
+  AccessPermission getAccessPermission(Address addr) {
+    Entry cache_entry := getCacheEntry(addr);
+    if(is_valid(cache_entry)) {
+      return L2Cache_State_to_permission(cache_entry.CacheState);
+    }
+
+    return AccessPermission:NotPresent;
+  }
+
+  void setAccessPermission(Entry cache_entry, Address addr, State state) {
+    if (is_valid(cache_entry)) {
+      cache_entry.changePermission(L2Cache_State_to_permission(state));
+    }
+  }
+
   void removeSharer(Address addr, NodeID id) {
 
     if (localDirectory.isTagPresent(addr)) {

diff --git a/src/mem/protocol/MOESI_CMP_token-dir.sm b/src/mem/protocol/MOESI_CMP_token-dir.sm
index aabde0af80159111eabefa07e2958345d729f11a..9ca0f1fc6a1e8bd7794a8a40166266568a8a42ad 100644 (file)
--- a/src/mem/protocol/MOESI_CMP_token-dir.sm
+++ b/src/mem/protocol/MOESI_CMP_token-dir.sm
@@ -199,7 +199,20 @@ machine(Directory, "Token protocol")
       // assert(getDirectoryEntry(addr).Tokens >= (max_tokens() / 2)); // Only mostly true; this might not always hold
     }
   }
-  
+
+  AccessPermission getAccessPermission(Address addr) {
+    TBE tbe := TBEs[addr];
+    if(is_valid(tbe)) {
+      return Directory_State_to_permission(tbe.TBEState);
+    }
+
+    return Directory_State_to_permission(getDirectoryEntry(addr).DirectoryState);
+  }
+
+  void setAccessPermission(Address addr, State state) {
+    getDirectoryEntry(addr).changePermission(Directory_State_to_permission(state));
+  }
+
   bool okToIssueStarving(Address addr, MachineID machinID) {
     return persistentTable.okToIssueStarving(addr, machineID);
   }

diff --git a/src/mem/protocol/MOESI_CMP_token-dma.sm b/src/mem/protocol/MOESI_CMP_token-dma.sm
index dfd26e64dea1435466307a4f6504bd4467fe7924..40b60490c923ddd2e9174a13409acc64e054d0d9 100644 (file)
--- a/src/mem/protocol/MOESI_CMP_token-dma.sm
+++ b/src/mem/protocol/MOESI_CMP_token-dma.sm
@@ -63,6 +63,13 @@ machine(DMA, "DMA Controller")
   cur_state := state;
   }
 
+  AccessPermission getAccessPermission(Address addr) {
+    return AccessPermission:NotPresent;
+  }
+
+  void setAccessPermission(Address addr, State state) {
+  }
+
   out_port(reqToDirectory_out, DMARequestMsg, reqToDirectory, desc="...");
 
   in_port(dmaRequestQueue_in, SequencerMsg, mandatoryQueue, desc="...") {

diff --git a/src/mem/protocol/MOESI_hammer-cache.sm b/src/mem/protocol/MOESI_hammer-cache.sm
index 24f3ab318c26dea6c75f260a5289810c9d6be508..6fe12d561dd33ae3d7d9d69de010142a5191c35c 100644 (file)
--- a/src/mem/protocol/MOESI_hammer-cache.sm
+++ b/src/mem/protocol/MOESI_hammer-cache.sm
@@ -227,6 +227,26 @@ machine(L1Cache, "AMD Hammer-like protocol")
     }
   }
 
+  AccessPermission getAccessPermission(Address addr) {
+    TBE tbe := TBEs[addr];
+    if(is_valid(tbe)) {
+      return L1Cache_State_to_permission(tbe.TBEState);
+    }
+
+    Entry cache_entry := getCacheEntry(addr);
+    if(is_valid(cache_entry)) {
+      return L1Cache_State_to_permission(cache_entry.CacheState);
+    }
+
+    return AccessPermission:NotPresent;
+  }
+
+  void setAccessPermission(Entry cache_entry, Address addr, State state) {
+    if (is_valid(cache_entry)) {
+      cache_entry.changePermission(L1Cache_State_to_permission(state));
+    }
+  }
+
   Event mandatory_request_type_to_event(RubyRequestType type) {
     if (type == RubyRequestType:LD) {
       return Event:Load;

diff --git a/src/mem/protocol/MOESI_hammer-dir.sm b/src/mem/protocol/MOESI_hammer-dir.sm
index 96af4228fbfe396c8acf5729fcd7afac169d801f..828c762cba7394a30e502100dbe8a53acaf0dfff 100644 (file)
--- a/src/mem/protocol/MOESI_hammer-dir.sm
+++ b/src/mem/protocol/MOESI_hammer-dir.sm
@@ -232,7 +232,20 @@ machine(Directory, "AMD Hammer-like protocol")
     }
     getDirectoryEntry(addr).DirectoryState := state;
   }
-  
+
+  AccessPermission getAccessPermission(Address addr) {
+    TBE tbe := TBEs[addr];
+    if(is_valid(tbe)) {
+      return Directory_State_to_permission(tbe.TBEState);
+    }
+
+    return Directory_State_to_permission(getDirectoryEntry(addr).DirectoryState);
+  }
+
+  void setAccessPermission(PfEntry pf_entry, Address addr, State state) {
+    getDirectoryEntry(addr).changePermission(Directory_State_to_permission(state));
+  }
+
   Event cache_request_to_event(CoherenceRequestType type) {
     if (type == CoherenceRequestType:GETS) {
       return Event:GETS;

diff --git a/src/mem/protocol/MOESI_hammer-dma.sm b/src/mem/protocol/MOESI_hammer-dma.sm
index c784fb6b987d0068018c8587c3166b2fed9324a1..f254c1633dbe529d3bde2a44ad6585b8758c56fa 100644 (file)
--- a/src/mem/protocol/MOESI_hammer-dma.sm
+++ b/src/mem/protocol/MOESI_hammer-dma.sm
@@ -60,6 +60,13 @@ machine(DMA, "DMA Controller")
     cur_state := state;
   }
 
+  AccessPermission getAccessPermission(Address addr) {
+    return AccessPermission:NotPresent;
+  }
+
+  void setAccessPermission(Address addr, State state) {
+  }
+
   out_port(reqToDirectory_out, DMARequestMsg, reqToDirectory, desc="...");
 
   in_port(dmaRequestQueue_in, SequencerMsg, mandatoryQueue, desc="...") {

diff --git a/src/mem/protocol/Network_test-cache.sm b/src/mem/protocol/Network_test-cache.sm
index e76c002f578ec99fc12f4fb4622a871ab9c1cc4f..b97819ca322ce06cae7920273e67b36270cbd6ff 100644 (file)
--- a/src/mem/protocol/Network_test-cache.sm
+++ b/src/mem/protocol/Network_test-cache.sm
@@ -120,6 +120,13 @@ machine(L1Cache, "Network_test L1 Cache")
 
   }
 
+  AccessPermission getAccessPermission(Address addr) {
+    return AccessPermission:NotPresent;
+  }
+
+  void setAccessPermission(Entry cache_entry, Address addr, State state) {
+  }
+
   Entry getCacheEntry(Address address), return_by_pointer="yes" {
     return OOD;
   }

diff --git a/src/mem/protocol/Network_test-dir.sm b/src/mem/protocol/Network_test-dir.sm
index c3e6dfaf051eb655d864c75c71859b5f2189d81e..593a409d0369ac9d1d411ff57a7ee8f462fd11b6 100644 (file)
--- a/src/mem/protocol/Network_test-dir.sm
+++ b/src/mem/protocol/Network_test-dir.sm
@@ -69,6 +69,13 @@ machine(Directory, "Network_test Directory")
 
   }
 
+  AccessPermission getAccessPermission(Address addr) {
+    return AccessPermission:NotPresent;
+  }
+
+  void setAccessPermission(Address addr, State state) {
+  }
+
   // ** IN_PORTS **
 
   in_port(requestQueue_in, RequestMsg, requestToDir) {

diff --git a/src/mem/protocol/RubySlicc_Types.sm b/src/mem/protocol/RubySlicc_Types.sm
index cf0f64500bb0476160cc04639f1686ac0ec62583..a2f8abfaa54545e21d19ecbcab882a4ff6118731 100644 (file)
--- a/src/mem/protocol/RubySlicc_Types.sm
+++ b/src/mem/protocol/RubySlicc_Types.sm
@@ -120,7 +120,9 @@ structure(RubyRequest, desc="...", interface="Message", external="yes") {
   int contextId,             desc="this goes away but must be replace with Nilay";
 }
 
-external_type(AbstractEntry, primitive="yes");
+structure(AbstractEntry, primitive="yes", external = "yes") {
+  void changePermission(AccessPermission);
+}
 
 structure (DirectoryMemory, external = "yes") {
   AbstractEntry lookup(Address);
@@ -128,7 +130,9 @@ structure (DirectoryMemory, external = "yes") {
   void invalidateBlock(Address);
 }
 
-external_type(AbstractCacheEntry, primitive="yes");
+structure(AbstractCacheEntry, primitive="yes", external = "yes") {
+  void changePermission(AccessPermission);
+}
 
 structure (CacheMemory, external = "yes") {
   bool cacheAvail(Address);

diff --git a/src/mem/ruby/slicc_interface/AbstractController.hh b/src/mem/ruby/slicc_interface/AbstractController.hh
index fcfe104b3345d34fc2ab179c578eb25da9c88441..eb8399af2152486fc3e7d5236f61ac0b8e9005f9 100644 (file)
--- a/src/mem/ruby/slicc_interface/AbstractController.hh
+++ b/src/mem/ruby/slicc_interface/AbstractController.hh
@@ -32,6 +32,7 @@
 #include <iostream>
 #include <string>
 
+#include "mem/protocol/AccessPermission.hh"
 #include "mem/protocol/MachineType.hh"
 #include "mem/ruby/common/Address.hh"
 #include "mem/ruby/common/Consumer.hh"
@@ -67,6 +68,9 @@ class AbstractController : public SimObject, public Consumer
     virtual void wakeup() = 0;
     //  virtual void dumpStats(std::ostream & out) = 0;
     virtual void clearStats() = 0;
+
+  private:
+    virtual AccessPermission getAccessPermission(Address addr) = 0;
 };
 
 #endif // __MEM_RUBY_SLICC_INTERFACE_ABSTRACTCONTROLLER_HH__

diff --git a/src/mem/slicc/ast/MethodCallExprAST.py b/src/mem/slicc/ast/MethodCallExprAST.py
index 6a2977533ebbc4c975eab09f59c088de680aaabe..cfee9b19dcfbcc1ec892fd1e3016885bf516ff04 100644 (file)
--- a/src/mem/slicc/ast/MethodCallExprAST.py
+++ b/src/mem/slicc/ast/MethodCallExprAST.py
@@ -160,7 +160,13 @@ class MemberMethodCallExprAST(MethodCallExprAST):
 
         if return_type.isInterface:
             prefix = "static_cast<%s &>" % return_type.c_ident
-        prefix = "%s((%s)." % (prefix, code)
+
+        if str(obj_type) == "AbstractCacheEntry" or \
+           ("interface" in obj_type and
+            obj_type["interface"] == "AbstractCacheEntry"):
+            prefix = "%s((*(%s))." % (prefix, code)
+        else:
+            prefix = "%s((%s)." % (prefix, code)
 
         return obj_type, methodId, prefix
 

diff --git a/src/mem/slicc/symbols/StateMachine.py b/src/mem/slicc/symbols/StateMachine.py
index 09e17aee95eeb4545a3a3046f933c82e264eb575..a3a95002d8208f493435a379e4456205e92e1561 100644 (file)
--- a/src/mem/slicc/symbols/StateMachine.py
+++ b/src/mem/slicc/symbols/StateMachine.py
@@ -348,8 +348,6 @@ static int m_num_controllers;
 // Set and Reset for cache_entry variable
 void set_cache_entry(${{self.EntryType.c_ident}}*& m_cache_entry_ptr, AbstractCacheEntry* m_new_cache_entry);
 void unset_cache_entry(${{self.EntryType.c_ident}}*& m_cache_entry_ptr);
-// Set permissions for the cache_entry
-void set_permission(${{self.EntryType.c_ident}}*& m_cache_entry_ptr, AccessPermission perm);
 ''')
 
         if self.TBEType != None:
@@ -864,15 +862,6 @@ $c_ident::unset_cache_entry(${{self.EntryType.c_ident}}*& m_cache_entry_ptr)
 {
   m_cache_entry_ptr = 0;
 }
-
-void
-$c_ident::set_permission(${{self.EntryType.c_ident}}*& m_cache_entry_ptr,
-                         AccessPermission perm)
-{
-    if (m_cache_entry_ptr != NULL) {
-       m_cache_entry_ptr->changePermission(perm);
-    }
-}
 ''')
 
         if self.TBEType != None:
@@ -1116,14 +1105,16 @@ ${ident}_Controller::doTransition(${ident}_Event event,
 ''')
         if self.TBEType != None and self.EntryType != None:
             code('setState(m_tbe_ptr, m_cache_entry_ptr, addr, next_state);')
-            code('set_permission(m_cache_entry_ptr, ${ident}_State_to_permission(next_state));')
+            code('setAccessPermission(m_cache_entry_ptr, addr, next_state);')
         elif self.TBEType != None:
             code('setState(m_tbe_ptr, addr, next_state);')
+            code('setAccessPermission(addr, next_state);')
         elif self.EntryType != None:
             code('setState(m_cache_entry_ptr, addr, next_state);')
-            code('set_permission(m_cache_entry_ptr, ${ident}_State_to_permission(next_state));')
+            code('setAccessPermission(m_cache_entry_ptr, addr, next_state);')
         else:
             code('setState(addr, next_state);')
+            code('setAccessPermission(addr, next_state);')
 
         code('''
     } else if (result == TransitionResult_ResourceStall) {