clkpart to analyse async flops too

diff --git a/passes/hierarchy/clkpart.cc b/passes/hierarchy/clkpart.cc
index b79625540d6a8a3741415c4a266874c8fabbc39a..15a5328b90cbbcdb7bedb4a5c1cf38b98505d6cf 100644 (file)
--- a/passes/hierarchy/clkpart.cc
+++ b/passes/hierarchy/clkpart.cc
@@ -161,6 +161,14 @@ struct ClkPartPass : public Pass {
                                        bool this_en_pol = !enable_mode || cell->type.in(ID($_DFFE_NP_), ID($_DFFE_PP_));
                                        key = clkdomain_t(this_clk_pol, assign_map(cell->getPort(ID(C))), this_en_pol, enable_mode ? assign_map(cell->getPort(ID(E))) : RTLIL::SigSpec());
                                }
+                               else
+                               if (cell->type.in(ID($_DFF_NN0_), ID($_DFF_NN1_), ID($_DFF_NP0_), ID($_DFF_NP1_),
+                                                       ID($_DFF_PN0_), ID($_DFF_PN1_), ID($_DFF_PP0_), ID($_DFF_PP1_)))
+                               {
+                                       bool this_clk_pol = cell->type.in(ID($_DFF_PN0_), ID($_DFF_PN1_), ID($_DFF_PP0_), ID($_DFF_PP1_));
+                                       log_assert(!enable_mode); // TODO
+                                       key = clkdomain_t(this_clk_pol, assign_map(cell->getPort(ID(C))), true, RTLIL::SigSpec());
+                               }
                                else
                                        continue;