* config/tc-arm.c: Likewise.
* config/tc-dlx.h: Likewise.
* config/tc-hppa.c: Likewise.
* config/tc-i386.c: Likewise.
* config/tc-m32r.c: Likewise.
* config/tc-m68hc11.c: Likewise.
* config/tc-m68k.c: Likewise.
* config/tc-m88k.c: Likewise.
* config/tc-mcore.c: Likewise.
* config/tc-mips.c: Likewise.
* config/tc-mmix.c: Likewise.
* config/tc-msp430.c: Likewise.
* config/tc-ns32k.c: Likewise.
* config/tc-or32.c: Likewise.
* config/tc-or32.h: Likewise.
* config/tc-pj.c: Likewise.
* config/tc-ppc.c: Likewise.
* config/tc-s390.c: Likewise.
* config/tc-sh64.c: Likewise.
* config/tc-sh.c: Likewise.
* config/tc-sparc.c: Likewise.
#define COFF_MAGIC SIPFBOMAGIC
/* Should the reloc be output ?
on the 29k, this is true only if there is a symbol attached.
- on the h8, this is allways true, since no fixup is done
+ on the h8, this is always true, since no fixup is done
*/
#define TC_COUNT_RELOC(x) (x->fx_addsy)
#define TC_CONS_RELOC RELOC_32
{"mla", 0xe0200090, 3, ARM_EXT_V2, do_mla},
{"mlas", 0xe0300090, 3, ARM_EXT_V2, do_mla},
- /* Generic copressor instructions. */
+ /* Generic coprocessor instructions. */
{"cdp", 0xee000000, 3, ARM_EXT_V2, do_cdp},
{"ldc", 0xec100000, 3, ARM_EXT_V2, do_lstc},
{"ldcl", 0xec500000, 3, ARM_EXT_V2, do_lstc},
if (!req_entry)
as_bad (_("unreq: missing hash entry for \"%s\""), name);
else if (req_entry->builtin)
- /* FIXME: We are deleteing a built in register alias which
+ /* FIXME: We are deleting a built in register alias which
points to a const data structure, so we only need to
free up the memory used by the key in the hash table.
Unfortunately we have not recorded this value, so this
;
else
{
- /* Deleteing a user defined alias. We need to free the
+ /* Deleting a user defined alias. We need to free the
key and the value, but fortunately the key is the same
as the value->name field. */
free ((char *) req_entry->name);
#define COFF_MAGIC DLXMAGIC
/* Should the reloc be output ?
on the 29k, this is true only if there is a symbol attached.
- on the h8, this is allways true, since no fixup is done
+ on the h8, this is always true, since no fixup is done
on dlx, I have no idea!! but lets keep it here just for fun.
*/
#define TC_COUNT_RELOC(x) (x->fx_addsy)
static void pa_vtable_inherit PARAMS ((int));
#endif
-/* File and gloally scoped variable declarations. */
+/* File and globally scoped variable declarations. */
#ifdef OBJ_SOM
/* Root and final entry in the space chain. */
if ((i.tm.cpu_flags & CpuPNI) && i.operands > 0)
{
- /* These Intel Precott New Instructions have the fixed
+ /* These Intel Prescott New Instructions have the fixed
operands with an opcode suffix which is coded in the same
place as an 8-bit immediate field would be. Here we check
those operands and remove them afterwards. */
char *errmsg;
char save_str2 = *str2;
- /* Seperate the two instructions. */
+ /* Separate the two instructions. */
*str2 = 0;
/* Make sure the two insns begin on a 32 bit boundary.
/* Initialize GAS's cgen interface for a new instruction. */
gas_cgen_init_parse ();
- /* Look for a parallel instruction seperator. */
+ /* Look for a parallel instruction separator. */
if ((str2 = strstr (str, "||")) != NULL)
{
assemble_two_insns (str, str2, 1);
return;
}
- /* Also look for a sequential instruction seperator. */
+ /* Also look for a sequential instruction separator. */
if ((str2 = strstr (str, "->")) != NULL)
{
assemble_two_insns (str, str2, 0);
static struct hash_control *m68hc11_hash;
/* Current cpu (either cpu6811 or cpu6812). This is determined automagically
- by 'get_default_target' by looking at default BFD vector. This is overriden
+ by 'get_default_target' by looking at default BFD vector. This is overridden
with the -m<cpu> option. */
static int current_architecture = 0;
fragS *frag;
int where;
- /* The relative branch convertion is not supported for
+ /* The relative branch conversion is not supported for
brclr and brset. */
assert ((opcode->format & M6811_OP_BITMASK) == 0);
assert (nb_operands == 1);
char *f;
unsigned long n;
- /* The relative branch convertion is not supported for
+ /* The relative branch conversion is not supported for
brclr and brset. */
assert ((opcode->format & M6811_OP_BITMASK) == 0);
assert (nb_operands == 2);
}
/* build_insn takes a pointer to the opcode entry in the opcode table,
- the array of operand expressions and builds the correspding instruction.
+ the array of operand expressions and builds the corresponding instruction.
This operation only deals with non relative jumps insn (need special
handling). */
static void
register unsigned char *opcode = fixP->fx_frag->fr_opcode;
/* Rewrite the PC relative instructions to absolute address ones.
- these are rumoured to be faster, and the apollo linker refuses
+ these are rumored to be faster, and the apollo linker refuses
to deal with the PC relative relocations. */
if (opcode[0] == 0x60 && opcode[1] == 0xff) /* BRA -> JMP. */
{
break;
}
- /* Figure out innner displacement stuff. */
+ /* Figure out inner displacement stuff. */
if (opP->mode == POST || opP->mode == PRE)
{
if (cpu_of_arch (current_architecture) & cpu32)
fragP->fr_opcode[1] = 0x06; /* Branch offset = 6. */
/* JF: these used to be fr_opcode[2,3], but they may be in a
- different frag, in which case refering to them is a no-no.
+ different frag, in which case referring to them is a no-no.
Only fr_opcode[0,1] are guaranteed to work. */
*buffer_address++ = 0x4e; /* put in jmp long (0x4ef9) */
*buffer_address++ = (char) 0xf9;
}
/* Skip ahead to a comma. This is used for OPT options which we do
- not suppor tand which take arguments. */
+ not support and which take arguments. */
static void
skip_to_comma (arg, on)
/* These functions are needed if we are linking with obj-coffbfd.c.
That file may be replaced by a more BFD oriented version at some
- point. If that happens, these functions should be rexamined.
+ point. If that happens, these functions should be reexamined.
Ian Lance Taylor, Cygnus Support, 13 July 1993. */
{
/* Scan forwards to find the name of the section. If the section
being switched to is ".line" then this is a DWARF1 debug section
- which is arbitarily placed inside generated code. In this case
+ which is arbitrarily placed inside generated code. In this case
do not dump the literal pool because it is a) inefficient and
b) would require the generation of extra code to jump around the
pool. */
variable. */
static offsetT mips_cprestore_offset = -1;
-/* Similiar for NewABI PIC code, where $gp is callee-saved. NewABI has some
+/* Similar for NewABI PIC code, where $gp is callee-saved. NewABI has some
more optimizations, it can use a register value instead of a memory-saved
offset and even an other register than $gp as global pointer. */
static offsetT mips_cpreturn_offset = -1;
/* The previous instruction reads the LO register; if the
current instruction writes to the LO register, we must
insert two NOPS. Some newer processors have interlocks.
- Also the tx39's multiply instructions can be exectuted
- immediatly after a read from HI/LO (without the delay),
+ Also the tx39's multiply instructions can be executed
+ immediately after a read from HI/LO (without the delay),
though the tx39's divide insns still do require the
delay. */
if (! (hilo_interlocks
&& ISA_HAS_COPROC_DELAYS (mips_opts.isa)
&& (pinfo & INSN_READ_COND_CODE))
/* We can not swap with an instruction that requires a
- delay slot, becase the target of the branch might
+ delay slot, because the target of the branch might
interfere with that instruction. */
|| (! mips_opts.mips16
&& ISA_HAS_COPROC_DELAYS (mips_opts.isa)
- 0x80000000);
}
- /* Right now, this routine can only handle signed 32-bit contants. */
+ /* Right now, this routine can only handle signed 32-bit constants. */
if (! IS_SEXT_32BIT_NUM(ep->X_add_number + 0x8000))
as_warn (_("operand overflow"));
: 0)
/* load_register()
- * This routine generates the least number of instructions neccessary to load
+ * This routine generates the least number of instructions necessary to load
* an absolute expression value into a register.
*/
static void
* This routine implements the seemingly endless macro or synthesized
* instructions and addressing modes in the mips assembly language. Many
* of these macros are simple and are similar to each other. These could
- * probably be handled by some kind of table or grammer aproach instead of
+ * probably be handled by some kind of table or grammar approach instead of
* this verbose method. Others are not simple macros but are more like
* optimizing code generation.
* One interesting optimization is when several store macros appear
- * consecutivly that would load AT with the upper half of the same address.
+ * consecutively that would load AT with the upper half of the same address.
* The ensuing load upper instructions are ommited. This implies some kind
* of global optimization. We currently only optimize within a single macro.
* For many of the load and store macros if the address is specified as a
expr1.X_add_symbol = NULL;
expr1.X_add_number = 1;
- /* Umatched fixups should not be put in the same frag as a relaxable
+ /* Unmatched fixups should not be put in the same frag as a relaxable
macro. For example, suppose we have:
lui $4,%hi(l1) # 1
files with -mabi=64, assembling them as o32 or n32 (with
-Wa,-32 or -Wa,-n32). This is not beautiful, but since
the whole kernel is loaded into a memory region that is
- addressible with sign-extended 32-bit addresses, it is
+ addressable with sign-extended 32-bit addresses, it is
wasteful to compute the upper 32 bits of every
non-literal address, that takes more space and time.
Some day this should probably be implemented as an
/*
- o Note that the assembler pulls down any immediately preceeding label
+ o Note that the assembler pulls down any immediately preceding label
to the aligned address.
o It's not documented but auto alignment is reinstated by
a .align pseudo instruction.
}
/* Handle the .cpreturn pseudo-op defined for NewABI PIC code. If an offset
- was given in the preceeding .cpsetup, it results in:
+ was given in the preceding .cpsetup, it results in:
ld $gp, offset($sp)
If a register $reg2 was given there, it results in:
#define STATE_GREG_UNDF ENCODE_RELAX (STATE_GREG, STATE_ZERO)
#define STATE_GREG_DEF ENCODE_RELAX (STATE_GREG, STATE_MAX)
-/* These displacements are relative to the adress following the opcode
+/* These displacements are relative to the address following the opcode
word of the instruction. The catch-all states have zero for "reach"
and "next" entries. */
break;
case mmix_operands_jmp:
- /* A JMP. Everyhing is already done. */
+ /* A JMP. Everything is already done. */
break;
case mmix_operands_roundregs:
{
/* Don't require non-register operands. Always generate
fixups, so we don't have to copy lots of code and create
- maintanance problems. TRIP is supposed to be a rare
+ maintenance problems. TRIP is supposed to be a rare
instruction, so the overhead should not matter. We
aren't allowed to fix_new_exp for an expression which is
an O_register at this point, however. */
res += msp430_dstoperand (&op2, l2, opcode->bin_opcode);
if (res)
- break; /* An error occured. All warnings were done before. */
+ break; /* An error occurred. All warnings were done before. */
bin |= (op2.reg | (op1.reg << 8) | (op1.am << 4) | (op2.am << 7));
res += msp430_dstoperand (&op2, l2, opcode->bin_opcode);
if (res)
- break; /* Error occured. All warnings were done before. */
+ break; /* Error occurred. All warnings were done before. */
bin |= (op2.reg | (op1.reg << 8) | (op1.am << 4) | (op2.am << 7));
mov r5,r6
jmp -2
- is equial to:
+ is equal to:
lab:
mov r5,r6
jmp lab
}
/* Now check constants. */
- /* Substitude register mode with a constant generator if applicable. */
+ /* Substitute register mode with a constant generator if applicable. */
x = (short) x; /* Extend sign. */
return 0;
}
- /* Check if inderect register mode @Rn / postincrement @Rn+. */
+ /* Check if indirect register mode @Rn / postincrement @Rn+. */
if (*l == '@')
{
char *t = l;
3, the entry is a pointer at a bignum struct
- The low-order-byte coresponds to low physical memory.
+ The low-order-byte corresponds to low physical memory.
Obviously a FRAGment must be created for each valid disp in PART whose
datalength is undefined (to bad) .
The case where just the expression is undefined is less severe and is
#define DOUBLE 2
#define UNDEF 3
/* Those limits are calculated from the displacement start in memory.
- The ns32k uses the begining of the instruction as displacement
+ The ns32k uses the beginning of the instruction as displacement
base. This type of displacements could be handled here by moving
the limit window up or down. I choose to use an internal
displacement base-adjust as there are other routines that must
case '+':
if (str[2] != '\000')
{
- addr_modeP->mode = 27; /* pc-relativ */
+ addr_modeP->mode = 27; /* pc-relative */
addr_modeP->disp[0] = str + 2;
return -1;
}
if (addr_modeP->mode == DEFAULT || addr_modeP->scaled_mode == -1)
{
- /* Resolve ambigious operands, this shouldn't be necessary if
+ /* Resolve ambiguous operands, this shouldn't be necessary if
one uses standard NSC operand syntax. But the sequent
- compiler doesn't!!! This finds a proper addressinging mode
+ compiler doesn't!!! This finds a proper addressing mode
if it is implicitly stated. See ns32k-opcode.h. */
(void) evaluate_expr (&exprP, ptr); /* This call takes time Sigh! */
Operands are parsed in such an order that the opcode is updated from
its most significant bit, that is when the operand need to alter the
opcode.
- Be carefull not to put to objects in the same iif-slot. */
+ Be careful not to put to objects in the same iif-slot. */
static void encode_operand
PARAMS ((int, char **, const char *, const char *, char, char));
freeptr++; /* OVE:this is an useful hack. */
sprintf (freeptr, "((%s-1)*%d)", argv[i], desc->im_size);
argv[i] = freeptr;
- pcrel -= 1; /* Make pcrel 0 inspite of what case 'p':
+ pcrel -= 1; /* Make pcrel 0 in spite of what case 'p':
wants. */
/* fall thru */
case 'p': /* Displacement - pc relative addressing. */
assembler. You only need to know if it's possible to reduce your
cpu-instruction to iif-format (takes some work) and adopt the other
md_? parts according to given instructions Note that iif was
- invented for the clean ns32k`s architecure. */
+ invented for the clean ns32k`s architecture. */
/* GAS for the ns32k has a problem. PC relative displacements are
relative to the address of the opcode, not the address of the
}
#endif /* OBJ_AOUT */
-#endif /* BFD_ASSMEBLER */
+#endif /* BFD_ASSEMBLER */
encode (&machine_opcodes[insn_index ("l.jalr")], &jalr_r9_opcode, 9, 'B');
}
-/* Returs non zero if instruction is to be used. */
+/* Returns non zero if instruction is to be used. */
static int
check_invalid_opcode (opcode)
#endif
/* Should the reloc be output ?
- on the 29k, this is true only if there is a symbol attatched.
- on the h8, this is allways true, since no fixup is done. */
+ on the 29k, this is true only if there is a symbol attached.
+ on the h8, this is always true, since no fixup is done. */
#define TC_COUNT_RELOC(x) (x->fx_addsy)
#define TC_CONS_RELOC RELOC_32
}
/* Insert names into the opcode table which are really mini macros,
- not opcodes. The fakeness is inidicated with an opcode of -1. */
+ not opcodes. The fakeness is indicated with an opcode of -1. */
static void
fake_opcode (name, func)
ppc_setup_opcodes ();
- /* Tell the main code what the endianness is if it is not overidden
+ /* Tell the main code what the endianness is if it is not overridden
by the user. */
if (!set_target_endian)
{
/* The .comm and .lcomm pseudo-ops for XCOFF. XCOFF puts common
symbols in the .bss segment as though they were local common
- symbols, and uses a different smclas. The native Aix 4.3.3 assember
+ symbols, and uses a different smclas. The native Aix 4.3.3 assembler
aligns .comm and .lcomm to 4 bytes. */
static void
/* The .function pseudo-op. This takes several arguments. The first
argument seems to be the external name of the symbol. The second
- argment seems to be the label for the start of the function. gcc
+ argument seems to be the label for the start of the function. gcc
uses the same name for both. I have no idea what the third and
fourth arguments are meant to be. The optional fifth argument is
an expression for the size of the function. In COFF this symbol
break;
case 'A':
- /* Option -A is deprecated. Still available for compatability. */
+ /* Option -A is deprecated. Still available for compatibility. */
if (arg != NULL && strcmp (arg, "esa") == 0)
current_cpu = S390_OPCODE_G5;
else if (arg != NULL && strcmp (arg, "esame") == 0)
/* After a displacement a block in parentheses can start. */
if (*str != '(')
{
- /* Check if parethesed block can be skipped. If the next
+ /* Check if parenthesized block can be skipped. If the next
operand is neiter an optional operand nor a base register
then we have a syntax error. */
operand = s390_operands + *(++opindex_ptr);
while (!(operand->flags & S390_OPERAND_BASE))
operand = s390_operands + *(++opindex_ptr);
- /* If there is a next operand it must be seperated by a comma. */
+ /* If there is a next operand it must be separated by a comma. */
if (opindex_ptr[1] != '\0')
{
if (*str++ != ',')
if (*str++ != ')')
as_bad (_("syntax error; missing ')' after base register"));
skip_optional = 0;
- /* If there is a next operand it must be seperated by a comma. */
+ /* If there is a next operand it must be separated by a comma. */
if (opindex_ptr[1] != '\0')
{
if (*str++ != ',')
as_bad (_("syntax error; ')' not allowed here"));
str++;
}
- /* If there is a next operand it must be seperated by a comma. */
+ /* If there is a next operand it must be separated by a comma. */
if (opindex_ptr[1] != '\0')
{
if (*str++ != ',')
static int preset_target_arch;
/* The bit mask of architectures that could
- accomodate the insns seen so far. */
+ accommodate the insns seen so far. */
static int valid_arch;
const char EXP_CHARS[] = "eE";
#define ENCODE_RELAX(what,length) (((what) << 4) + (length))
#define GET_WHAT(x) ((x>>4))
-/* These are the three types of relaxable instrction. */
+/* These are the three types of relaxable instruction. */
/* These are the types of relaxable instructions; except for END which is
a marker. */
#define COND_JUMP 1
no matter if expr is a constant, or a more complex
expression, e.g. sym-. or sym1-sym2.
However, we also used to accept @(sym,pc)
- as adressing sym, i.e. meaning the same as plain sym.
+ as addressing sym, i.e. meaning the same as plain sym.
Some existing code does use the @(sym,pc) syntax, so
we give it the old semantics for now, but warn about
its use, so that users have some time to fix their code.
}
/* This static variable is set by s_uacons to tell sh_cons_align that
- the expession does not need to be aligned. */
+ the expression does not need to be aligned. */
static int sh_no_align_cons = 0;
case BFD_RELOC_SH_PCRELIMM8BY4:
/* The lower two bits of the PC are cleared before the
displacement is added in. We can assume that the destination
- is on a 4 byte bounday. If this instruction is also on a 4
+ is on a 4 byte boundary. If this instruction is also on a 4
byte boundary, then we want
(target - here) / 4
and target - here is a multiple of 4.
/* The machine independent code will convert CMP/EQ into cmp/EQ
because it thinks the '/' is the end of the symbol. Moreover,
all but the first sub-insn is a parallel processing insn won't
- be capitailzed. Instead of hacking up the machine independent
+ be capitalized. Instead of hacking up the machine independent
code, we just deal with it here. */
c = TOLOWER (c);
name[nlen] = c;
{NULL, NULL, NULL},
};
\f
-/* sparc64 priviledged registers. */
+/* sparc64 privileged registers. */
struct priv_reg_entry
{
}
}
-/* Handle the .empty pseudo-op. This supresses the warnings about
+/* Handle the .empty pseudo-op. This suppresses the warnings about
invalid delay slot usage. */
static void
}
/* This static variable is set by s_uacons to tell sparc_cons_align
- that the expession does not need to be aligned. */
+ that the expression does not need to be aligned. */
static int sparc_no_align_cons = 0;
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