Move abc9.* constpad entries to Abc9Pass::on_register()

diff --git a/kernel/yosys.cc b/kernel/yosys.cc
index 6956cbdc3bc8f48eb59981c1e4cc5ddbbd6bf1f6..8190d89028eb4ca553932977adb992379558b047 100644 (file)
--- a/kernel/yosys.cc
+++ b/kernel/yosys.cc
@@ -524,41 +524,6 @@ void yosys_setup()
                PyRun_SimpleString("import sys");
        #endif
 
-       RTLIL::constpad["abc9.script.default"] = "&scorr; &sweep; &dc2; &dch -f; &ps; &if {C} {W} {D} {R} -v; &mfs";
-       RTLIL::constpad["abc9.script.default.area"] = "&scorr; &sweep; &dc2; &dch -f; &ps; &if {C} {W} {D} {R} -a -v; &mfs";
-       RTLIL::constpad["abc9.script.default.fast"] = "&if {C} {W} {D} {R}";
-       // Based on ABC's &flow
-       RTLIL::constpad["abc9.script.flow"] = "&scorr; &sweep;" \
-               /* Round 1 */ \
-               "&unmap; &if {C} {W} {D} {R}; &mfs;" \
-               "&st; &dsdb;" \
-               "&unmap; &if {C} {W} {D} {R}; &mfs;" \
-               "&st; &syn2 -m -R 10; &dsdb;" \
-               "&blut -a -K 6;" \
-               "&unmap; &if {C} {W} {D} {R}; &mfs;" \
-               /* Round 2 */ \
-               "&st; &sopb;" \
-               "&unmap; &if {C} {W} {D} {R}; &mfs;" \
-               "&st; &dsdb;" \
-               "&unmap; &if {C} {W} {D} {R}; &mfs;" \
-               "&st; &syn2 -m -R 10; &dsdb;" \
-               "&blut -a -K 6;" \
-               "&unmap; &if {C} {W} {D} {R} -v; &mfs";
-       // Based on ABC's &flow2
-       RTLIL::constpad["abc9.script.flow2"] = "&scorr; &sweep;" \
-               /* Comm1 */ "&synch2 -K 6 -C 500; &if -m {C} {W} {D} {R} -v; &mfs "/*"-W 4 -M 500 -C 7000"*/"; &save;"\
-               /* Comm2 */ "&dch -C 500; &if -m {C} {W} {D} {R} -v; &mfs "/*"-W 4 -M 500 -C 7000"*/"; &save;"\
-               "&load; &st; &sopb -R 10 -C 4; " \
-               /* Comm3 */ "&synch2 -K 6 -C 500; &if -m "/*"-E 5"*/" {C} {W} {D} {R} -v; &mfs "/*"-W 4 -M 500 -C 7000"*/"; &save;"\
-               /* Comm2 */ "&dch -C 500; &if -m {C} {W} {D} {R} -v; &mfs "/*"-W 4 -M 500 -C 7000"*/"; &save; "\
-               "&load";
-       // Based on ABC's &flow3
-       RTLIL::constpad["abc9.script.flow3"] = "&scorr; &sweep;" \
-               "&if {C} {W} {D}; &save; &st; &syn2; &if {C} {W} {D} {R} -v; &save; &load;"\
-               "&st; &if {C} -g -K 6; &dch -f; &if {C} {W} {D} {R} -v; &save; &load;"\
-               "&st; &if {C} -g -K 6; &synch2; &if {C} {W} {D} {R} -v; &save; &load;"\
-               "&mfs";
-
        Pass::init_register();
        yosys_design = new RTLIL::Design;
        yosys_celltypes.setup();

diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index 3fdcc0e5c00fe7d128438c652018b2565522ff30..3f05494c769c0da8997d141b1ff9ddb81f71f17a 100644 (file)
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -735,6 +735,43 @@ clone_lut:
 
 struct Abc9Pass : public Pass {
        Abc9Pass() : Pass("abc9", "use ABC9 for technology mapping") { }
+       void on_register() YS_OVERRIDE
+       {
+               RTLIL::constpad["abc9.script.default"] = "&scorr; &sweep; &dc2; &dch -f; &ps; &if {C} {W} {D} {R} -v; &mfs";
+               RTLIL::constpad["abc9.script.default.area"] = "&scorr; &sweep; &dc2; &dch -f; &ps; &if {C} {W} {D} {R} -a -v; &mfs";
+               RTLIL::constpad["abc9.script.default.fast"] = "&if {C} {W} {D} {R}";
+               // Based on ABC's &flow
+               RTLIL::constpad["abc9.script.flow"] = "&scorr; &sweep;" \
+                       /* Round 1 */ \
+                       "&unmap; &if {C} {W} {D} {R}; &mfs;" \
+                       "&st; &dsdb;" \
+                       "&unmap; &if {C} {W} {D} {R}; &mfs;" \
+                       "&st; &syn2 -m -R 10; &dsdb;" \
+                       "&blut -a -K 6;" \
+                       "&unmap; &if {C} {W} {D} {R}; &mfs;" \
+                       /* Round 2 */ \
+                       "&st; &sopb;" \
+                       "&unmap; &if {C} {W} {D} {R}; &mfs;" \
+                       "&st; &dsdb;" \
+                       "&unmap; &if {C} {W} {D} {R}; &mfs;" \
+                       "&st; &syn2 -m -R 10; &dsdb;" \
+                       "&blut -a -K 6;" \
+                       "&unmap; &if {C} {W} {D} {R} -v; &mfs";
+               // Based on ABC's &flow2
+               RTLIL::constpad["abc9.script.flow2"] = "&scorr; &sweep;" \
+                       /* Comm1 */ "&synch2 -K 6 -C 500; &if -m {C} {W} {D} {R} -v; &mfs "/*"-W 4 -M 500 -C 7000"*/"; &save;"\
+                       /* Comm2 */ "&dch -C 500; &if -m {C} {W} {D} {R} -v; &mfs "/*"-W 4 -M 500 -C 7000"*/"; &save;"\
+                       "&load; &st; &sopb -R 10 -C 4; " \
+                       /* Comm3 */ "&synch2 -K 6 -C 500; &if -m "/*"-E 5"*/" {C} {W} {D} {R} -v; &mfs "/*"-W 4 -M 500 -C 7000"*/"; &save;"\
+                       /* Comm2 */ "&dch -C 500; &if -m {C} {W} {D} {R} -v; &mfs "/*"-W 4 -M 500 -C 7000"*/"; &save; "\
+                       "&load";
+               // Based on ABC's &flow3
+               RTLIL::constpad["abc9.script.flow3"] = "&scorr; &sweep;" \
+                       "&if {C} {W} {D}; &save; &st; &syn2; &if {C} {W} {D} {R} -v; &save; &load;"\
+                       "&st; &if {C} -g -K 6; &dch -f; &if {C} {W} {D} {R} -v; &save; &load;"\
+                       "&st; &if {C} -g -K 6; &synch2; &if {C} {W} {D} {R} -v; &save; &load;"\
+                       "&mfs";
+       }
        void help() YS_OVERRIDE
        {
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