liteXXX cores: share same methodology for on-board tests
authorFlorent Kermarrec <florent@enjoy-digital.fr>
Sun, 1 Mar 2015 10:07:28 +0000 (11:07 +0100)
committerFlorent Kermarrec <florent@enjoy-digital.fr>
Sun, 1 Mar 2015 10:21:12 +0000 (11:21 +0100)
misoclib/com/liteeth/README
misoclib/com/liteeth/example_designs/test/make.py
misoclib/mem/litesata/README
misoclib/mem/litesata/example_designs/test/bist.py
misoclib/mem/litesata/example_designs/test/config.py [deleted file]
misoclib/mem/litesata/example_designs/test/make.py [new file with mode: 0644]
misoclib/mem/litesata/example_designs/test/test_la.py
misoclib/mem/litesata/example_designs/test/test_regs.py
misoclib/tools/litescope/README
misoclib/tools/litescope/example_designs/test/make.py

index 715ca343cc8ccf15ee7ebc898bf62efb471adf01..e49b8eed308c25d75320b17ddbfd203c9c72f149 100644 (file)
@@ -72,7 +72,7 @@ devel [AT] lists.m-labs.hk.
 5. Test design (only for KC705 for now):
   try to ping 192.168.1.40
   go to [..]/example_designs/test/
-  run ./make.py udp
+  run ./make.py test_udp
 
 6. Build and load Etherbone design (only for KC705 for now):
   python3 make.py -t etherbone all load-bitstream
@@ -80,7 +80,7 @@ devel [AT] lists.m-labs.hk.
 7. Test design (only for KC705 for now):
   try to ping 192.168.1.40
   go to [..]/example_designs/test/
-  run ./make.py etherbone
+  run ./make.py test_etherbone
 
 [> Simulations:
   Simulations are available in misoclib/com/liteeth/test/:
index ee69f8660528d4bb1586cda465883b84c859e507..54f2ca45f079f7db84f7ca25cc5f85943328dd10 100644 (file)
@@ -29,5 +29,5 @@ if __name__ == "__main__":
                return importlib.import_module(name)
 
        for test in args.test:
-               t = _import("test_"+test)
+               t = _import(test)
                t.main(wb)
index 436451c9453200e1bf357468f71ad4d872774e81..0aa28667649abf6f02696acd3e4a6e2ba27ed254 100644 (file)
@@ -100,7 +100,7 @@ devel [AT] lists.m-labs.hk.
 
 6. Test design (only for KC705 for now):
   go to [..]/example_designs/test/
-  run ./make.py --port your_serial_port bist
+  run ./bist.py --port your_serial_port
 
 7. If you only want to build the core and use it with your
    regular design flow:
index 9d863a784296de1383ae9fd39c45fc8d8ca615e5..9d45ca2d78c2a420215cc5002fa7a8b9b57542eb 100644 (file)
@@ -2,7 +2,7 @@ import time
 import argparse
 import random as rand
 from collections import OrderedDict
-from config import *
+from misoclib.tools.litescope.host.driver.uart import LiteScopeUARTDriver
 
 KB = 1024
 MB = 1024*KB
@@ -128,6 +128,9 @@ def _get_args():
                description="""\
 SATA BIST utility.
 """)
+       parser.add_argument("--port", default=2, help="UART port")
+       parser.add_argument("--baudrate", default=921600, help="UART baudrate")
+       parser.add_argument("--busword", default=32, help="CSR busword")
        parser.add_argument("-s", "--transfer_size", default=1024, help="transfer sizes (in KB, up to 16MB)")
        parser.add_argument("-l", "--total_length", default=256, help="total transfer length (in MB, up to HDD capacity)")
        parser.add_argument("-n", "--loops", default=1, help="number of loop per transfer (allow more precision on speed calculation for small transfers)")
@@ -140,6 +143,7 @@ SATA BIST utility.
 
 if __name__ == "__main__":
        args = _get_args()
+       wb = LiteScopeUARTDriver(args.port, args.baudrate, "./csr.csv", int(args.busword), debug=False)
        wb.open()
        ###
        identify = LiteSATABISTIdentifyDriver(wb.regs, "sata_bist")
diff --git a/misoclib/mem/litesata/example_designs/test/config.py b/misoclib/mem/litesata/example_designs/test/config.py
deleted file mode 100644 (file)
index cdde349..0000000
+++ /dev/null
@@ -1,9 +0,0 @@
-from litescope.host.driver.uart import LiteScopeUARTDriver
-
-csr_csv_file = "./csr.csv"
-busword = 32
-debug_wb = False
-
-com = 2
-baud = 921600
-wb = LiteScopeUARTDriver(com, baud, csr_csv_file, busword, debug_wb)
\ No newline at end of file
diff --git a/misoclib/mem/litesata/example_designs/test/make.py b/misoclib/mem/litesata/example_designs/test/make.py
new file mode 100644 (file)
index 0000000..54f2ca4
--- /dev/null
@@ -0,0 +1,33 @@
+#!/usr/bin/env python3
+import argparse, importlib
+
+def _get_args():
+       parser = argparse.ArgumentParser()
+       parser.add_argument("-b", "--bridge", default="uart", help="Bridge to use")
+       parser.add_argument("--port", default=2, help="UART port")
+       parser.add_argument("--baudrate", default=921600, help="UART baudrate")
+       parser.add_argument("--ip_address", default="192.168.1.40", help="Etherbone  IP address")
+       parser.add_argument("--udp_port", default=20000, help="Etherbone UDP port")
+       parser.add_argument("--busword", default=32, help="CSR busword")
+
+       parser.add_argument("test", nargs="+", help="specify a test")
+
+       return parser.parse_args()
+
+if __name__ == "__main__":
+       args = _get_args()
+       if args.bridge == "uart":
+               from misoclib.tools.litescope.host.driver.uart import LiteScopeUARTDriver
+               wb = LiteScopeUARTDriver(args.port, args.baudrate, "./csr.csv", int(args.busword), debug=False)
+       elif args.bridge == "etherbone":
+               from misoclib.tools.litescope.host.driver.etherbone import LiteScopeEtherboneDriver
+               wb = LiteScopeEtherboneDriver(args.ip_address, int(args.udp_port), "./csr.csv", int(args.busword), debug=False)
+       else:
+               ValueError("Invalid bridge {}".format(args.bridge))
+
+       def _import(name):
+               return importlib.import_module(name)
+
+       for test in args.test:
+               t = _import(test)
+               t.main(wb)
index f0344d6eec2d7f71673d3e5b467e884a8074055e..0fb17a761368b448045c254098f683e7b467a486 100644 (file)
@@ -1,71 +1,71 @@
 import sys
-from config import *
 from tools import *
-from bist import *
+from test_bist import *
 from litescope.host.driver.la import LiteScopeLADriver
 
-la = LiteScopeLADriver(wb.regs, "la")
-identify = LiteSATABISTIdentifyDriver(wb.regs, "sata_bist")
-generator = LiteSATABISTGeneratorDriver(wb.regs, "sata_bist")
-checker = LiteSATABISTCheckerDriver(wb.regs, "sata_bist")
-wb.open()
-regs = wb.regs
-###
+def main(wb):
+       la = LiteScopeLADriver(wb.regs, "la")
+       identify = LiteSATABISTIdentifyDriver(wb.regs, "sata_bist")
+       generator = LiteSATABISTGeneratorDriver(wb.regs, "sata_bist")
+       checker = LiteSATABISTCheckerDriver(wb.regs, "sata_bist")
+       wb.open()
+       regs = wb.regs
+       ###
 
-trig = "now"
-if len(sys.argv) < 2:
-       print("No trigger condition, triggering immediately!")
-else:
-       trig = sys.argv[1]
+       trig = "now"
+       if len(sys.argv) < 2:
+               print("No trigger condition, triggering immediately!")
+       else:
+               trig = sys.argv[1]
 
-conditions = {}
-conditions["now"] = {}
-conditions["id_cmd"] = {
-       "sata_command_tx_sink_stb"                              : 1,
-       "sata_command_tx_sink_payload_identify" : 1,
-}
-conditions["id_resp"] = {
-       "source_source_payload_data" : primitives["X_RDY"],
-}
-conditions["wr_cmd"] = {
-       "sata_command_tx_sink_stb"                      : 1,
-       "sata_command_tx_sink_payload_write"    : 1,
-}
-conditions["wr_resp"] = {
-       "sata_command_rx_source_stb"                    : 1,
-       "sata_command_rx_source_payload_write"  : 1,
-}
-conditions["rd_cmd"] = {
-       "sata_command_tx_sink_stb"                      : 1,
-       "sata_command_tx_sink_payload_read"     : 1,
-}
-conditions["rd_resp"] = {
-       "sata_command_rx_source_stb"                    : 1,
-       "sata_command_rx_source_payload_read"   : 1,
-}
+       conditions = {}
+       conditions["now"] = {}
+       conditions["id_cmd"] = {
+               "sata_command_tx_sink_stb"                              : 1,
+               "sata_command_tx_sink_payload_identify" : 1,
+       }
+       conditions["id_resp"] = {
+               "source_source_payload_data" : primitives["X_RDY"],
+       }
+       conditions["wr_cmd"] = {
+               "sata_command_tx_sink_stb"                      : 1,
+               "sata_command_tx_sink_payload_write"    : 1,
+       }
+       conditions["wr_resp"] = {
+               "sata_command_rx_source_stb"                    : 1,
+               "sata_command_rx_source_payload_write"  : 1,
+       }
+       conditions["rd_cmd"] = {
+               "sata_command_tx_sink_stb"                      : 1,
+               "sata_command_tx_sink_payload_read"     : 1,
+       }
+       conditions["rd_resp"] = {
+               "sata_command_rx_source_stb"                    : 1,
+               "sata_command_rx_source_payload_read"   : 1,
+       }
 
-la.configure_term(port=0, cond=conditions[trig])
-la.configure_sum("term")
+       la.configure_term(port=0, cond=conditions[trig])
+       la.configure_sum("term")
 
-# Run Logic Analyzer
-la.run(offset=64, length=1024)
+       # Run Logic Analyzer
+       la.run(offset=64, length=1024)
 
-#identify.run(blocking=False)
-generator.run(0, 2, 1, 0, blocking=False)
-#checker.run(0, 2, 1, 0, blocking=False)
+       #identify.run(blocking=False)
+       generator.run(0, 2, 1, 0, blocking=False)
+       #checker.run(0, 2, 1, 0, blocking=False)
 
-while not la.done():
-       pass
+       while not la.done():
+               pass
 
-la.upload()
-la.save("dump.vcd")
-###
-wb.close()
+       la.upload()
+       la.save("dump.vcd")
+       ###
+       wb.close()
 
-f = open("dump_link.txt", "w")
-data = link_trace(la,
-       tx_data_name="sink_sink_payload_data",
-       rx_data_name="source_source_payload_data"
-)
-f.write(data)
-f.close()
+       f = open("dump_link.txt", "w")
+       data = link_trace(la,
+               tx_data_name="sink_sink_payload_data",
+               rx_data_name="source_source_payload_data"
+       )
+       f.write(data)
+       f.close()
index 982f849c55d6dec445559248114f463d5a8488e9..c0ef387fea4cb528dd64ef2121e2e2e914db64bc 100644 (file)
@@ -1,10 +1,9 @@
-from config import *
-
-wb.open()
-regs = wb.regs
-###
-print("sysid     : 0x%04x" %regs.identifier_sysid.read())
-print("revision  : 0x%04x" %regs.identifier_revision.read())
-print("frequency : %d MHz" %(regs.identifier_frequency.read()/1000000))
-###
-wb.close()
+def main(wb):
+       wb.open()
+       regs = wb.regs
+       ###
+       print("sysid     : 0x%04x" %regs.identifier_sysid.read())
+       print("revision  : 0x%04x" %regs.identifier_revision.read())
+       print("frequency : %d MHz" %(regs.identifier_frequency.read()/1000000))
+       ###
+       wb.close()
index a246c3dc4cf94efd34bc8ac49bef1e95c113579e..00a8668b853fc4c740bf0b39c38683ea64ec4f21 100644 (file)
@@ -91,12 +91,12 @@ devel [AT] lists.m-labs.hk.
 
 5. Test design:
   go to [..]/example_designs/test/ and run:
-  ./make.py --port your_serial_port io (will blink leds)
-  ./make.py --port your_serial_port la (will capture counter)
+  ./make.py --port your_serial_port test_io (will blink leds)
+  ./make.py --port your_serial_port test_la (will capture counter)
 
   tests can also be executed over Etherbone (provided with LiteEth):
-  ./make.py --ip_address fpga_ip_address io
-  ./make.py --ip_address fpga_ip_address la
+  ./make.py --ip_address fpga_ip_address test_io
+  ./make.py --ip_address fpga_ip_address test_la
 
 [> Simulations:
   XXX convert simulations
index 335623c05bf8ddd63de025eb4a18d1081775901b..676356fecaaec72e5946f7069d72c0447e6ada61 100644 (file)
@@ -29,5 +29,5 @@ if __name__ == "__main__":
                return importlib.import_module(name)
 
        for test in args.test:
-               t = _import("test_"+test)
+               t = _import(test)
                t.main(wb)