projects / openpower-isa.git / commitdiff
? search:
summary | shortlog | log | commit | commitdiff | tree
raw | patch | inline | side by side (parent: b63dea0)
remove use of sv.lfssh, replace with sv.lfs/els element strided
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 12 Aug 2022 11:12:16 +0000 (12:12 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Fri, 12 Aug 2022 11:12:20 +0000 (12:12 +0100)
src/openpower/decoder/isa/test_caller_svp64_dct.py patch | blob | history

diff --git a/src/openpower/decoder/isa/test_caller_svp64_dct.py b/src/openpower/decoder/isa/test_caller_svp64_dct.py
index 8541a81ec3a86eb8007a068f918c2f7b69b6d219..9a8c1158bafc111fa6d0d0d4d26a541d1040590b 100644 (file)
--- a/src/openpower/decoder/isa/test_caller_svp64_dct.py
+++ b/src/openpower/decoder/isa/test_caller_svp64_dct.py
@@ -925,7 +925,7 @@ class DCTTestCase(FHDLTestCase):
         """>>> lst = [# LOAD bit-reversed with half-swap
                       "svshape 8, 1, 1, 6, 0",
                       "svremap 1, 0, 0, 0, 0, 0, 0",
-                      "sv.lfssh *0, 4(1), 2",
+                      "sv.lfs/els *0, 4(1)",
                       # Inner butterfly, twin +/- MUL-ADD-SUB
                       "svremap 31, 1, 0, 2, 0, 1, 1",
                       "svshape 8, 1, 1, 4, 0",
@@ -943,7 +943,7 @@ class DCTTestCase(FHDLTestCase):
         lst = SVP64Asm( ["addi 1, 0, 0x000",
                          "svshape 8, 1, 1, 6, 0",
                          "svremap 1, 0, 0, 0, 0, 0, 0",
-                         "sv.lfssh *0, 4(1), 2",
+                         "sv.lfs/els *0, 4(1)",
                          "svremap 31, 1, 0, 2, 0, 1, 1",
                          "svshape 8, 1, 1, 4, 0",
                          "sv.fdmadds *0, *0, *0, *8",
@@ -1015,7 +1015,7 @@ class DCTTestCase(FHDLTestCase):
         """>>> lst = [# LOAD bit-reversed with half-swap
                       "svshape 8, 1, 1, 14, 0",
                       "svremap 1, 0, 0, 0, 0, 0, 0",
-                      "sv.lfssh *0, 4(1), 2",
+                      "sv.lfs/els *0, 4(1)",
                       # Outer butterfly, iterative sum
                       "svremap 31, 0, 1, 2, 1, 0, 1",
                       "svshape 8, 1, 1, 11, 0",
@@ -1033,7 +1033,7 @@ class DCTTestCase(FHDLTestCase):
         lst = SVP64Asm( ["addi 1, 0, 0x000",
                          "svshape 8, 1, 1, 14, 0",
                          "svremap 1, 0, 0, 0, 0, 0, 0",
-                         "sv.lfssh *0, 4(1), 2",
+                         "sv.lfs/els *0, 4(1)",
                          "svremap 31, 0, 1, 2, 1, 0, 1",
                          "svshape 8, 1, 1, 11, 0",
                          "sv.fadds *0, *0, *0",