add pdepd/pextd

diff --git a/openpower/isa/fixedlogical.mdwn b/openpower/isa/fixedlogical.mdwn
index b2bba382f66b7a962a43d4a0ee0735078ead416c..01eeffb1defc5255faea6b16c52a26e2c3a23bd4 100644 (file)
--- a/openpower/isa/fixedlogical.mdwn
+++ b/openpower/isa/fixedlogical.mdwn
@@ -535,3 +535,49 @@ Pseudo-code:
 Special Registers Altered:
 
     None
+
+# Parallel Bits Extract Doubleword
+
+X-Form
+
+* pextd RA,RS,RB
+
+Pseudo-code:
+
+    result[0:63] <- 0
+    mask <- (RB)
+    m <- 0
+    k <- 0
+    do while m < 64
+        if (RB)[63-m] = 1 then
+            result[63-k] <- (RS)[63-m]
+            k <- k + 1
+        m <- m + 1
+    RA <- result
+
+Special Registers Altered:
+
+    None
+
+# Parallel Bits Deposit Doubleword
+
+X-Form
+
+* pdepd RA,RS,RB
+
+Pseudo-code:
+
+    result[0:63] <- 0
+    mask <- (RB)
+    m <- 0
+    k <- 0
+    do while m < 64
+        if (RB)[63-m] = 1 then
+            result[63-m] <- (RS)[63-k]
+            k <- k + 1
+        m <- m + 1
+    RA <- result
+
+Special Registers Altered:
+
+    None

diff --git a/openpower/isatables/RM-1P-2S1D.csv b/openpower/isatables/RM-1P-2S1D.csv
index 75ee3ac13b56d07ac52968c5dd4377e24ccd5f34..f61cd27f66164d90ceef4f46e77ef4cabbdfb09c 100644 (file)
--- a/openpower/isatables/RM-1P-2S1D.csv
+++ b/openpower/isatables/RM-1P-2S1D.csv
@@ -16,7 +16,9 @@ cmpeqb,CROP,,1P,EXTRA3,NO,d:BF,s:RA,s:RB,0,RA,RB,0,0,0,BF,0
 4/0=ftdiv,NORMAL,,1P,EXTRA3,NO,d:BF,s:FRA,s:FRB,0,FRA,FRB,0,0,0,BF,0
 bmask,NORMAL,,1P,EXTRA3,NO,d:RT,s:RA,s:RB,0,RA,RB,0,RT,0,0,0
 cntlzdm,NORMAL,,1P,EXTRA3,NO,d:RT,s:RA,s:RB,0,RS,RB,0,RA,0,0,0
+pdepd,NORMAL,,1P,EXTRA3,NO,d:RT,s:RA,s:RB,0,RS,RB,0,RA,0,0,0
 addex,NORMAL,,1P,EXTRA3,NO,d:RT,s:RA,s:RB,0,RA,RB,0,RT,0,0,0
+pextd,NORMAL,,1P,EXTRA3,NO,d:RT,s:RA,s:RB,0,RS,RB,0,RA,0,0,0
 cfuged,NORMAL,,1P,EXTRA3,NO,d:RT,s:RA,s:RB,0,RS,RB,0,RA,0,0,0
 bpermd,NORMAL,,1P,EXTRA3,NO,d:RA,s:RS,s:RB,0,RS,RB,0,RA,0,0,0
 modud,NORMAL,,1P,EXTRA3,NO,d:RT,s:RA,s:RB,0,RA,RB,0,RT,0,0,0

diff --git a/openpower/isatables/minor_31.csv b/openpower/isatables/minor_31.csv
index b77193ab0d27eb0d73c9df66097c0108db0d6017..de280854c0d91298364a7644b71e14e57f490fcf 100644 (file)
--- a/openpower/isatables/minor_31.csv
+++ b/openpower/isatables/minor_31.csv
@@ -156,6 +156,8 @@ opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry ou
 0b0001111100,LOGICAL,OP_OR,RS,RB,NONE,RA,NONE,CR0,0,1,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,nor,X,,,
 0b0110111100,LOGICAL,OP_OR,RS,RB,NONE,RA,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,or,X,,,
 0b0110011100,LOGICAL,OP_OR,RS,RB,NONE,RA,NONE,CR0,1,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,orc,X,,,
+0b0010011100,LOGICAL,OP_PDEP,RS,RB,NONE,RA,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,pdepd,X,,0,
+0b0010111100,LOGICAL,OP_PEXT,RS,RB,NONE,RA,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,pextd,X,,0,
 0b0001111010,LOGICAL,OP_POPCNT,RS,NONE,NONE,RA,NONE,NONE,0,0,ZERO,0,is1B,0,0,0,0,0,0,NONE,0,0,popcntb,X,,,
 0b0111111010,LOGICAL,OP_POPCNT,RS,NONE,NONE,RA,NONE,NONE,0,0,ZERO,0,is8B,0,0,0,0,0,0,NONE,0,0,popcntd,X,,,
 0b0101111010,LOGICAL,OP_POPCNT,RS,NONE,NONE,RA,NONE,NONE,0,0,ZERO,0,is4B,0,0,0,0,0,0,NONE,0,0,popcntw,X,,,

diff --git a/src/openpower/decoder/isa/caller.py b/src/openpower/decoder/isa/caller.py
index 4e12c4d4e05abe96f7a290acbb78a492cd9ff571..6ae8d6e0f8a2711c431f3c1c03a80fa647f6582c 100644 (file)
--- a/src/openpower/decoder/isa/caller.py
+++ b/src/openpower/decoder/isa/caller.py
@@ -1969,7 +1969,7 @@ class ISACaller(ISACallerHelper, ISAFPHelpers, StepLoop):
                        "ctfpr", "ctfprs",
                        "mtfpr", "mtfprs",
                        "maddsubrs", "maddrs", "msubrs",
-                       "cfuged", "cntlzdm", "cnttzdm",
+                       "cfuged", "cntlzdm", "cnttzdm", "pdepd", "pextd",
                        ]:
             illegal = False
             ins_name = dotstrp

diff --git a/src/openpower/decoder/power_enums.py b/src/openpower/decoder/power_enums.py
index 54959a29b981ef5a9c1aa4c043c32741c7a2face..6ebe1f3b8877020bbfcb614be71f3f052efd8403 100644 (file)
--- a/src/openpower/decoder/power_enums.py
+++ b/src/openpower/decoder/power_enums.py
@@ -804,6 +804,7 @@ _insns = [
     "nop",
     "nor", "or", "orc", "ori", "oris",
     "pcdec",
+    "pdepd", "pextd",
     "popcntb", "popcntd", "popcntw",
     "prtyd", "prtyw",
     "rfid",
@@ -959,6 +960,8 @@ class MicrOp(Enum):
     OP_MSUBRS = 106
     OP_BYTEREV = 107
     OP_CFUGE = 108
+    OP_PDEP = 109
+    OP_PEXT = 110
 
 
 class SelType(Enum):

diff --git a/src/openpower/test/logical/logical_cases.py b/src/openpower/test/logical/logical_cases.py
index 809096e68d4c1ef05ff523fdad19ce5f3eea0b4e..3a8798ae64a4b39404acdf983dff1e51bc5391ad 100644 (file)
--- a/src/openpower/test/logical/logical_cases.py
+++ b/src/openpower/test/logical/logical_cases.py
@@ -190,3 +190,43 @@ class LogicalTestCase(TestAccumulatorBase):
                     case_idx=case_idx, RS_in=hex(gprs[4]),
                     RB_in=hex(gprs[5]), expected_RA=hex(e.intregs[3])):
                 self.add_case(prog, gprs, expected=e)
+
+    def case_pdepd(self):
+        prog = Program(list(SVP64Asm(["pdepd 3,4,5"])), bigendian)
+        for case_idx in range(200):
+            gprs = [0] * 32
+            gprs[4] = hash_256(f"pdepd {case_idx} r4") % 2**64
+            gprs[5] = hash_256(f"pdepd {case_idx} r5") % 2**64
+            e = ExpectedState(pc=4, int_regs=gprs)
+            e.intregs[3] = 0
+            j = 0
+            for i in range(64):
+                bit = 1 << i
+                if gprs[5] & bit:
+                    if gprs[4] & (1 << j):
+                        e.intregs[3] |= bit
+                    j += 1
+            with self.subTest(
+                    case_idx=case_idx, RS_in=hex(gprs[4]),
+                    RB_in=hex(gprs[5]), expected_RA=hex(e.intregs[3])):
+                self.add_case(prog, gprs, expected=e)
+
+    def case_pextd(self):
+        prog = Program(list(SVP64Asm(["pextd 3,4,5"])), bigendian)
+        for case_idx in range(200):
+            gprs = [0] * 32
+            gprs[4] = hash_256(f"pextd {case_idx} r4") % 2**64
+            gprs[5] = hash_256(f"pextd {case_idx} r5") % 2**64
+            e = ExpectedState(pc=4, int_regs=gprs)
+            e.intregs[3] = 0
+            j = 0
+            for i in range(64):
+                bit = 1 << i
+                if gprs[5] & bit:
+                    if gprs[4] & bit:
+                        e.intregs[3] |= 1 << j
+                    j += 1
+            with self.subTest(
+                    case_idx=case_idx, RS_in=hex(gprs[4]),
+                    RB_in=hex(gprs[5]), expected_RA=hex(e.intregs[3])):
+                self.add_case(prog, gprs, expected=e)