2013-11-11 Catherine Moore <clm@codesourcery.com>

	gas/
	* config/mips/tc-mips.c (convert_reg_type): Use
	INSN_LOAD_MEMORY instead of INSN_LOAD_MEMORY_DELAY.
	(reg_needs_delay): Likewise.
	(insns_between): Likewise.

	include/
	* opcode/mips.h (INSN_LOAD_MEMORY_DELAY): Rename to...
	(INSN_LOAD_MEMORY): ...this.

	opcodes/
	* mips-dis.c (print_insn_mips): Use
	INSN_LOAD_MEMORY instead of INSN_LOAD_MEMORY_DELAY.
	(print_insn_micromips): Likewise.
	* mips-opc.c (LDD): Remove.
	(CLD): Include INSN_LOAD_MEMORY.
	(LM): New.
	(mips_builtin_opcodes): Use LM instead of LDD.
        Add LM to load instructions.

diff --git a/ChangeLog b/ChangeLog
index 7f696273903738266dad95f21423e1e973febae5..97db6fd193347353d4bb5da2a7febb120bd96ffd 100644 (file)
--- a/ChangeLog
+++ b/ChangeLog
@@ -1,3 +1,25 @@
+2013-11-11  Catherine Moore  <clm@codesourcery.com>
+
+       gas/
+       * config/mips/tc-mips.c (convert_reg_type): Use
+       INSN_LOAD_MEMORY instead of INSN_LOAD_MEMORY_DELAY.
+       (reg_needs_delay): Likewise.
+       (insns_between): Likewise.
+
+       include/
+       * opcode/mips.h (INSN_LOAD_MEMORY_DELAY): Rename to...
+       (INSN_LOAD_MEMORY): ...this.
+
+       opcodes/
+       * mips-dis.c (print_insn_mips): Use
+       INSN_LOAD_MEMORY instead of INSN_LOAD_MEMORY_DELAY.
+       (print_insn_micromips): Likewise.
+       * mips-opc.c (LDD): Remove.
+       (CLD): Include INSN_LOAD_MEMORY.
+       (LM): New.
+       (mips_builtin_opcodes): Use LM instead of LDD.
+        Add LM to load instructions.
+
 2013-11-07  Thomas Schwinge  <thomas@codesourcery.com>
 
        * Makefile.in: Regenerate.

diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c
index 08ad7bab665b38133913336ae204d0d1033c6969..fcf06ac145376bf414298c9302ee7f1430b61879 100644 (file)
--- a/gas/config/tc-mips.c
+++ b/gas/config/tc-mips.c
@@ -491,7 +491,7 @@ static int mips_32bitmode = 0;
 /* Whether the processor uses hardware interlocks to protect reads
    from the GPRs after they are loaded from memory, and thus does not
    require nops to be inserted.  This applies to instructions marked
-   INSN_LOAD_MEMORY_DELAY.  These nops are only required at MIPS ISA
+   INSN_LOAD_MEMORY.  These nops are only required at MIPS ISA
    level I and microMIPS mode instructions are always interlocked.  */
 #define gpr_interlocks                                \
   (mips_opts.isa != ISA_MIPS1                         \
@@ -4389,7 +4389,7 @@ convert_reg_type (const struct mips_opcode *opcode,
          && (opcode->pinfo & (INSN_COPROC_MOVE_DELAY
                               | INSN_COPROC_MEMORY_DELAY
                               | INSN_LOAD_COPROC_DELAY
-                              | INSN_LOAD_MEMORY_DELAY
+                              | INSN_LOAD_MEMORY
                               | INSN_STORE_MEMORY)))
        return RTYPE_FPU | RTYPE_VEC;
       return RTYPE_FPU;
@@ -5529,7 +5529,7 @@ reg_needs_delay (unsigned int reg)
 
   prev_pinfo = history[0].insn_mo->pinfo;
   if (!mips_opts.noreorder
-      && (((prev_pinfo & INSN_LOAD_MEMORY_DELAY) && !gpr_interlocks)
+      && (((prev_pinfo & INSN_LOAD_MEMORY) && !gpr_interlocks)
          || ((prev_pinfo & INSN_LOAD_COPROC_DELAY) && !cop_interlocks))
       && (gpr_write_mask (&history[0]) & (1 << reg)))
     return TRUE;
@@ -5633,7 +5633,7 @@ insns_between (const struct mips_cl_insn *insn1,
       /* Check for GPR or coprocessor load delays.  All such delays
         are on the RT register.  */
       /* Itbl support may require additional care here.  */
-      if ((!gpr_interlocks && (pinfo1 & INSN_LOAD_MEMORY_DELAY))
+      if ((!gpr_interlocks && (pinfo1 & INSN_LOAD_MEMORY))
          || (!cop_interlocks && (pinfo1 & INSN_LOAD_COPROC_DELAY)))
        {
          if (insn2 == NULL || (gpr_read_mask (insn2) & gpr_write_mask (insn1)))

diff --git a/include/opcode/mips.h b/include/opcode/mips.h
index cb16d2a45e4bfb73015b08e65a99233387397838..c9dc52b8b85eca441bb8d30ca04b11c550bbba56 100644 (file)
--- a/include/opcode/mips.h
+++ b/include/opcode/mips.h
@@ -973,8 +973,8 @@ struct mips_opcode
 #define INSN_TLB                    0x00000200
 /* Reads coprocessor register other than floating point register.  */
 #define INSN_COP                    0x00000400
-/* Instruction loads value from memory, requiring delay.  */
-#define INSN_LOAD_MEMORY_DELAY      0x00000800
+/* Instruction loads value from memory.  */
+#define INSN_LOAD_MEMORY           0x00000800
 /* Instruction loads value from coprocessor, requiring delay.  */
 #define INSN_LOAD_COPROC_DELAY     0x00001000
 /* Instruction has unconditional branch delay slot.  */

diff --git a/opcodes/mips-dis.c b/opcodes/mips-dis.c
index 72f307f2f5130ec9fa4c088ac613d1a0cff8641a..1929ffcac95a7a85c512a5fcc2f5278426e4043a 100644 (file)
--- a/opcodes/mips-dis.c
+++ b/opcodes/mips-dis.c
@@ -1451,7 +1451,7 @@ print_insn_mips (bfd_vma memaddr,
                  info->branch_delay_insns = 1;
                }
              else if ((op->pinfo & (INSN_STORE_MEMORY
-                                    | INSN_LOAD_MEMORY_DELAY)) != 0)
+                                    | INSN_LOAD_MEMORY)) != 0)
                info->insn_type = dis_dref;
 
              infprintf (is, "%s", op->name);
@@ -2004,7 +2004,7 @@ print_insn_micromips (bfd_vma memaddr, struct disassemble_info *info)
                info->insn_type = dis_condbranch;
            }
          else if ((op->pinfo
-                   & (INSN_STORE_MEMORY | INSN_LOAD_MEMORY_DELAY)) != 0)
+                   & (INSN_STORE_MEMORY | INSN_LOAD_MEMORY)) != 0)
            info->insn_type = dis_dref;
 
          return length;

diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c
index 4f729313ed5352b58b32f44d2800a4dd1bd30e57..43fab35d50dd8f544ba45e676062eec3040f798e 100644 (file)
--- a/opcodes/mips-opc.c
+++ b/opcodes/mips-opc.c
@@ -192,15 +192,15 @@ decode_mips_operand (const char *p)
 
 /* Short hand so the lines aren't too long.  */
 
-#define LDD     INSN_LOAD_MEMORY_DELAY
 #define LCD    INSN_LOAD_COPROC_DELAY
 #define UBD     INSN_UNCOND_BRANCH_DELAY
 #define CBD    INSN_COND_BRANCH_DELAY
 #define COD     INSN_COPROC_MOVE_DELAY
-#define CLD    INSN_COPROC_MEMORY_DELAY
+#define CLD    (INSN_LOAD_MEMORY|INSN_COPROC_MEMORY_DELAY)
 #define CBL    INSN_COND_BRANCH_LIKELY
 #define NODS   INSN_NO_DELAY_SLOT
 #define TRAP   INSN_NO_DELAY_SLOT
+#define LM     INSN_LOAD_MEMORY
 #define SM     INSN_STORE_MEMORY
 
 #define WR_1   INSN_WRITE_1
@@ -380,9 +380,9 @@ const struct mips_opcode mips_builtin_opcodes[] =
    them first.  The assemblers uses a hash table based on the
    instruction name anyhow.  */
 /* name,               args,           match,      mask,       pinfo,                  pinfo2,         membership,     ase,    exclusions */
-{"pref",               "k,o(b)",       0xcc000000, 0xfc000000, RD_3,                   0,              I4_32|G3,       0,      0 },
+{"pref",               "k,o(b)",       0xcc000000, 0xfc000000, RD_3|LM,                0,              I4_32|G3,       0,      0 },
 {"pref",               "k,A(b)",       0,    (int) M_PREF_AB,  INSN_MACRO,             0,              I4_32|G3,       0,      0 },
-{"prefx",              "h,t(b)",       0x4c00000f, 0xfc0007ff, RD_2|RD_3|FP_S,         0,              I4_33,          0,      0 },
+{"prefx",              "h,t(b)",       0x4c00000f, 0xfc0007ff, RD_2|RD_3|FP_S|LM,              0,              I4_33,          0,      0 },
 {"nop",                        "",             0x00000000, 0xffffffff, 0,                      INSN2_ALIAS,    I1,             0,      0 }, /* sll */
 {"ssnop",              "",             0x00000040, 0xffffffff, 0,                      INSN2_ALIAS,    I1,             0,      0 }, /* sll */
 {"ehb",                        "",             0x000000c0, 0xffffffff, 0,                      INSN2_ALIAS,    I1,             0,      0 }, /* sll */
@@ -406,14 +406,14 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"ramri",              "d,s",          0x700000f5, 0xfc1f07ff, WR_1|RD_2,              0,              IL3A,           0,      0 },
 {"gsle",               "s,t",          0x70000026, 0xfc00ffff, RD_1|RD_2,              0,              IL3A,           0,      0 },
 {"gsgt",               "s,t",          0x70000027, 0xfc00ffff, RD_1|RD_2,              0,              IL3A,           0,      0 },
-{"gslble",             "t,b,d",        0xc8000010, 0xfc0007ff, WR_1|RD_2|RD_3|LDD,     0,              IL3A,           0,      0 },
-{"gslbgt",             "t,b,d",        0xc8000011, 0xfc0007ff, WR_1|RD_2|RD_3|LDD,     0,              IL3A,           0,      0 },
-{"gslhle",             "t,b,d",        0xc8000012, 0xfc0007ff, WR_1|RD_2|RD_3|LDD,     0,              IL3A,           0,      0 },
-{"gslhgt",             "t,b,d",        0xc8000013, 0xfc0007ff, WR_1|RD_2|RD_3|LDD,     0,              IL3A,           0,      0 },
-{"gslwle",             "t,b,d",        0xc8000014, 0xfc0007ff, WR_1|RD_2|RD_3|LDD,     0,              IL3A,           0,      0 },
-{"gslwgt",             "t,b,d",        0xc8000015, 0xfc0007ff, WR_1|RD_2|RD_3|LDD,     0,              IL3A,           0,      0 },
-{"gsldle",             "t,b,d",        0xc8000016, 0xfc0007ff, WR_1|RD_2|RD_3|LDD,     0,              IL3A,           0,      0 },
-{"gsldgt",             "t,b,d",        0xc8000017, 0xfc0007ff, WR_1|RD_2|RD_3|LDD,     0,              IL3A,           0,      0 },
+{"gslble",             "t,b,d",        0xc8000010, 0xfc0007ff, WR_1|RD_2|RD_3|LM,      0,              IL3A,           0,      0 },
+{"gslbgt",             "t,b,d",        0xc8000011, 0xfc0007ff, WR_1|RD_2|RD_3|LM,      0,              IL3A,           0,      0 },
+{"gslhle",             "t,b,d",        0xc8000012, 0xfc0007ff, WR_1|RD_2|RD_3|LM,      0,              IL3A,           0,      0 },
+{"gslhgt",             "t,b,d",        0xc8000013, 0xfc0007ff, WR_1|RD_2|RD_3|LM,      0,              IL3A,           0,      0 },
+{"gslwle",             "t,b,d",        0xc8000014, 0xfc0007ff, WR_1|RD_2|RD_3|LM,      0,              IL3A,           0,      0 },
+{"gslwgt",             "t,b,d",        0xc8000015, 0xfc0007ff, WR_1|RD_2|RD_3|LM,      0,              IL3A,           0,      0 },
+{"gsldle",             "t,b,d",        0xc8000016, 0xfc0007ff, WR_1|RD_2|RD_3|LM,      0,              IL3A,           0,      0 },
+{"gsldgt",             "t,b,d",        0xc8000017, 0xfc0007ff, WR_1|RD_2|RD_3|LM,      0,              IL3A,           0,      0 },
 {"gssble",             "t,b,d",        0xe8000010, 0xfc0007ff, RD_1|RD_2|RD_3|SM,      0,              IL3A,           0,      0 },
 {"gssbgt",             "t,b,d",        0xe8000011, 0xfc0007ff, RD_1|RD_2|RD_3|SM,      0,              IL3A,           0,      0 },
 {"gsshle",             "t,b,d",        0xe8000012, 0xfc0007ff, RD_1|RD_2|RD_3|SM,      0,              IL3A,           0,      0 },
@@ -422,37 +422,37 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"gsswgt",             "t,b,d",        0xe8000015, 0xfc0007ff, RD_1|RD_2|RD_3|SM,      0,              IL3A,           0,      0 },
 {"gssdle",             "t,b,d",        0xe8000016, 0xfc0007ff, RD_1|RD_2|RD_3|SM,      0,              IL3A,           0,      0 },
 {"gssdgt",             "t,b,d",        0xe8000017, 0xfc0007ff, RD_1|RD_2|RD_3|SM,      0,              IL3A,           0,      0 },
-{"gslwlec1",           "T,b,d",        0xc8000018, 0xfc0007ff, WR_1|RD_2|RD_3|LDD,     0,              IL3A,           0,      0 },
-{"gslwgtc1",           "T,b,d",        0xc8000019, 0xfc0007ff, WR_1|RD_2|RD_3|LDD,     0,              IL3A,           0,      0 },
-{"gsldlec1",           "T,b,d",        0xc800001a, 0xfc0007ff, WR_1|RD_2|RD_3|LDD,     0,              IL3A,           0,      0 },
-{"gsldgtc1",           "T,b,d",        0xc800001b, 0xfc0007ff, WR_1|RD_2|RD_3|LDD,     0,              IL3A,           0,      0 },
+{"gslwlec1",           "T,b,d",        0xc8000018, 0xfc0007ff, WR_1|RD_2|RD_3|LM,      0,              IL3A,           0,      0 },
+{"gslwgtc1",           "T,b,d",        0xc8000019, 0xfc0007ff, WR_1|RD_2|RD_3|LM,      0,              IL3A,           0,      0 },
+{"gsldlec1",           "T,b,d",        0xc800001a, 0xfc0007ff, WR_1|RD_2|RD_3|LM,      0,              IL3A,           0,      0 },
+{"gsldgtc1",           "T,b,d",        0xc800001b, 0xfc0007ff, WR_1|RD_2|RD_3|LM,      0,              IL3A,           0,      0 },
 {"gsswlec1",           "T,b,d",        0xe800001c, 0xfc0007ff, RD_1|RD_2|RD_3|SM,      0,              IL3A,           0,      0 },
 {"gsswgtc1",           "T,b,d",        0xe800001d, 0xfc0007ff, RD_1|RD_2|RD_3|SM,      0,              IL3A,           0,      0 },
 {"gssdlec1",           "T,b,d",        0xe800001e, 0xfc0007ff, RD_1|RD_2|RD_3|SM,      0,              IL3A,           0,      0 },
 {"gssdgtc1",           "T,b,d",        0xe800001f, 0xfc0007ff, RD_1|RD_2|RD_3|SM,      0,              IL3A,           0,      0 },
-{"gslwlc1",            "T,+a(b)",      0xc8000004, 0xfc00c03f, WR_1|RD_3|LDD,          0,              IL3A,           0,      0 },
-{"gslwrc1",            "T,+a(b)",      0xc8000005, 0xfc00c03f, WR_1|RD_3|LDD,          0,              IL3A,           0,      0 },
-{"gsldlc1",            "T,+a(b)",      0xc8000006, 0xfc00c03f, WR_1|RD_3|LDD,          0,              IL3A,           0,      0 },
-{"gsldrc1",            "T,+a(b)",      0xc8000007, 0xfc00c03f, WR_1|RD_3|LDD,          0,              IL3A,           0,      0 },
+{"gslwlc1",            "T,+a(b)",      0xc8000004, 0xfc00c03f, WR_1|RD_3|LM,           0,              IL3A,           0,      0 },
+{"gslwrc1",            "T,+a(b)",      0xc8000005, 0xfc00c03f, WR_1|RD_3|LM,           0,              IL3A,           0,      0 },
+{"gsldlc1",            "T,+a(b)",      0xc8000006, 0xfc00c03f, WR_1|RD_3|LM,           0,              IL3A,           0,      0 },
+{"gsldrc1",            "T,+a(b)",      0xc8000007, 0xfc00c03f, WR_1|RD_3|LM,           0,              IL3A,           0,      0 },
 {"gsswlc1",            "T,+a(b)",      0xe8000004, 0xfc00c03f, RD_1|RD_3|SM,           0,              IL3A,           0,      0 },
 {"gsswrc1",            "T,+a(b)",      0xe8000005, 0xfc00c03f, RD_1|RD_3|SM,           0,              IL3A,           0,      0 },
 {"gssdlc1",            "T,+a(b)",      0xe8000006, 0xfc00c03f, RD_1|RD_3|SM,           0,              IL3A,           0,      0 },
 {"gssdrc1",            "T,+a(b)",      0xe8000007, 0xfc00c03f, RD_1|RD_3|SM,           0,              IL3A,           0,      0 },
-{"gslbx",              "t,+b(b,d)",    0xd8000000, 0xfc000007, WR_1|RD_3|RD_4|LDD,     0,              IL3A,           0,      0 },
-{"gslhx",              "t,+b(b,d)",    0xd8000001, 0xfc000007, WR_1|RD_3|RD_4|LDD,     0,              IL3A,           0,      0 },
-{"gslwx",              "t,+b(b,d)",    0xd8000002, 0xfc000007, WR_1|RD_3|RD_4|LDD,     0,              IL3A,           0,      0 },
-{"gsldx",              "t,+b(b,d)",    0xd8000003, 0xfc000007, WR_1|RD_3|RD_4|LDD,     0,              IL3A,           0,      0 },
+{"gslbx",              "t,+b(b,d)",    0xd8000000, 0xfc000007, WR_1|RD_3|RD_4|LM,      0,              IL3A,           0,      0 },
+{"gslhx",              "t,+b(b,d)",    0xd8000001, 0xfc000007, WR_1|RD_3|RD_4|LM,      0,              IL3A,           0,      0 },
+{"gslwx",              "t,+b(b,d)",    0xd8000002, 0xfc000007, WR_1|RD_3|RD_4|LM,      0,              IL3A,           0,      0 },
+{"gsldx",              "t,+b(b,d)",    0xd8000003, 0xfc000007, WR_1|RD_3|RD_4|LM,      0,              IL3A,           0,      0 },
 {"gssbx",              "t,+b(b,d)",    0xf8000000, 0xfc000007, RD_1|RD_3|RD_4|SM,      0,              IL3A,           0,      0 },
 {"gsshx",              "t,+b(b,d)",    0xf8000001, 0xfc000007, RD_1|RD_3|RD_4|SM,      0,              IL3A,           0,      0 },
 {"gsswx",              "t,+b(b,d)",    0xf8000002, 0xfc000007, RD_1|RD_3|RD_4|SM,      0,              IL3A,           0,      0 },
 {"gssdx",              "t,+b(b,d)",    0xf8000003, 0xfc000007, RD_1|RD_3|RD_4|SM,      0,              IL3A,           0,      0 },
-{"gslwxc1",            "T,+b(b,d)",    0xd8000006, 0xfc000007, WR_1|RD_3|RD_4|LDD,     0,              IL3A,           0,      0 },
-{"gsldxc1",            "T,+b(b,d)",    0xd8000007, 0xfc000007, WR_1|RD_3|RD_4|LDD,     0,              IL3A,           0,      0 },
+{"gslwxc1",            "T,+b(b,d)",    0xd8000006, 0xfc000007, WR_1|RD_3|RD_4|LM,      0,              IL3A,           0,      0 },
+{"gsldxc1",            "T,+b(b,d)",    0xd8000007, 0xfc000007, WR_1|RD_3|RD_4|LM,      0,              IL3A,           0,      0 },
 {"gsswxc1",            "T,+b(b,d)",    0xf8000006, 0xfc000007, RD_1|RD_3|RD_4|SM,      0,              IL3A,           0,      0 },
 {"gssdxc1",            "T,+b(b,d)",    0xf8000007, 0xfc000007, RD_1|RD_3|RD_4|SM,      0,              IL3A,           0,      0 },
-{"gslq",               "+z,t,+c(b)",   0xc8000020, 0xfc008020, WR_1|WR_2|RD_4|LDD,     0,              IL3A,           0,      0 },
+{"gslq",               "+z,t,+c(b)",   0xc8000020, 0xfc008020, WR_1|WR_2|RD_4|LM,      0,              IL3A,           0,      0 },
 {"gssq",               "+z,t,+c(b)",   0xe8000020, 0xfc008020, RD_1|RD_2|RD_4|SM,      0,              IL3A,           0,      0 },
-{"gslqc1",             "+Z,T,+c(b)",   0xc8008020, 0xfc008020, WR_1|WR_2|RD_4|LDD,     0,              IL3A,           0,      0 },
+{"gslqc1",             "+Z,T,+c(b)",   0xc8008020, 0xfc008020, WR_1|WR_2|RD_4|LM,      0,              IL3A,           0,      0 },
 {"gssqc1",             "+Z,T,+c(b)",   0xe8008020, 0xfc008020, RD_1|RD_2|RD_4|SM,      0,              IL3A,           0,      0 },
 
 /* R5900 VU0 Macromode instructions. */
@@ -591,7 +591,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"abs.d",              "D,V",          0x46200005, 0xffff003f, WR_1|RD_2|FP_D,         0,              I1,             0,      SF },
 {"abs.ps",             "D,V",          0x46c00005, 0xffff003f, WR_1|RD_2|FP_D,         0,              I5_33|IL2F,     0,      0 },
 {"abs.ps",             "D,V",          0x45600005, 0xffff003f, WR_1|RD_2|FP_D,         0,              IL2E,           0,      0 },
-{"aclr",               "\\,~(b)",      0x04070000, 0xfc1f8000, RD_3|SM|NODS,           0,              0,              MC,     0 },
+{"aclr",               "\\,~(b)",      0x04070000, 0xfc1f8000, RD_3|LM|SM|NODS,        0,              0,              MC,     0 },
 {"aclr",               "\\,A(b)",      0,    (int) M_ACLR_AB,  INSN_MACRO,             0,              0,              MC,     0 },
 {"add",                        "d,v,t",        0x00000020, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              I1,             0,      0 },
 {"add",                        "t,r,I",        0,    (int) M_ADD_I,    INSN_MACRO,             0,              I1,             0,      0 },
@@ -630,7 +630,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"and.ob",             "D,S,Q",        0x4800000c, 0xfc20003f, WR_1|RD_2|RD_3|FP_D,    0,              N54,            0,      0 },
 {"and.qh",             "X,Y,Q",        0x7820000c, 0xfc20003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              MX,     0 },
 {"andi",               "t,r,i",        0x30000000, 0xfc000000, WR_1|RD_2,              0,              I1,             0,      0 },
-{"aset",               "\\,~(b)",      0x04078000, 0xfc1f8000, RD_3|SM|NODS,           0,              0,              MC,     0 },
+{"aset",               "\\,~(b)",      0x04078000, 0xfc1f8000, RD_3|LM|SM|NODS,        0,              0,              MC,     0 },
 {"aset",               "\\,A(b)",      0,    (int) M_ASET_AB,  INSN_MACRO,             0,              0,              MC,     0 },
 {"baddu",              "d,v,t",        0x70000028, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              IOCT,           0,      0 },
 /* b is at the top of the table.  */
@@ -1136,36 +1136,36 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"jal",                        "a",            0x0c000000, 0xfc000000, WR_31|UBD,              0,              I1,             0,      0 },
 {"jalx",               "+i",           0x74000000, 0xfc000000, WR_31|UBD,              0,              I1,             0,      0 },
 {"la",                 "t,A(b)",       0,    (int) M_LA_AB,    INSN_MACRO,             0,              I1,             0,      0 },
-{"laa",                        "d,(b),t",      0x7000049f, 0xfc0007ff, WR_1|RD_2|RD_3|LDD|SM,  0,              IOCT2,          0,      0 },
-{"laad",               "d,(b),t",      0x700004df, 0xfc0007ff, WR_1|RD_2|RD_3|LDD|SM,  0,              IOCT2,          0,      0 },
-{"lac",                        "d,(b)",        0x7000039f, 0xfc1f07ff, WR_1|RD_2|LDD|SM,       0,              IOCT2,          0,      0 },
-{"lacd",               "d,(b)",        0x700003df, 0xfc1f07ff, WR_1|RD_2|LDD|SM,       0,              IOCT2,          0,      0 },
-{"lad",                        "d,(b)",        0x7000019f, 0xfc1f07ff, WR_1|RD_2|LDD|SM,       0,              IOCT2,          0,      0 },
-{"ladd",               "d,(b)",        0x700001df, 0xfc1f07ff, WR_1|RD_2|LDD|SM,       0,              IOCT2,          0,      0 },
-{"lai",                        "d,(b)",        0x7000009f, 0xfc1f07ff, WR_1|RD_2|LDD|SM,       0,              IOCT2,          0,      0 },
-{"laid",               "d,(b)",        0x700000df, 0xfc1f07ff, WR_1|RD_2|LDD|SM,       0,              IOCT2,          0,      0 },
-{"las",                        "d,(b)",        0x7000029f, 0xfc1f07ff, WR_1|RD_2|LDD|SM,       0,              IOCT2,          0,      0 },
-{"lasd",               "d,(b)",        0x700002df, 0xfc1f07ff, WR_1|RD_2|LDD|SM,       0,              IOCT2,          0,      0 },
-{"law",                        "d,(b),t",      0x7000059f, 0xfc0007ff, WR_1|RD_2|RD_3|LDD|SM,  0,              IOCT2,          0,      0 },
-{"lawd",               "d,(b),t",      0x700005df, 0xfc0007ff, WR_1|RD_2|RD_3|LDD|SM,  0,              IOCT2,          0,      0 },
-{"lb",                 "t,o(b)",       0x80000000, 0xfc000000, WR_1|RD_3|LDD,          0,              I1,             0,      0 },
+{"laa",                        "d,(b),t",      0x7000049f, 0xfc0007ff, WR_1|RD_2|RD_3|LM|SM,   0,              IOCT2,          0,      0 },
+{"laad",               "d,(b),t",      0x700004df, 0xfc0007ff, WR_1|RD_2|RD_3|LM|SM,   0,              IOCT2,          0,      0 },
+{"lac",                        "d,(b)",        0x7000039f, 0xfc1f07ff, WR_1|RD_2|LM|SM,        0,              IOCT2,          0,      0 },
+{"lacd",               "d,(b)",        0x700003df, 0xfc1f07ff, WR_1|RD_2|LM|SM,        0,              IOCT2,          0,      0 },
+{"lad",                        "d,(b)",        0x7000019f, 0xfc1f07ff, WR_1|RD_2|LM|SM,        0,              IOCT2,          0,      0 },
+{"ladd",               "d,(b)",        0x700001df, 0xfc1f07ff, WR_1|RD_2|LM|SM,        0,              IOCT2,          0,      0 },
+{"lai",                        "d,(b)",        0x7000009f, 0xfc1f07ff, WR_1|RD_2|LM|SM,        0,              IOCT2,          0,      0 },
+{"laid",               "d,(b)",        0x700000df, 0xfc1f07ff, WR_1|RD_2|LM|SM,        0,              IOCT2,          0,      0 },
+{"las",                        "d,(b)",        0x7000029f, 0xfc1f07ff, WR_1|RD_2|LM|SM,        0,              IOCT2,          0,      0 },
+{"lasd",               "d,(b)",        0x700002df, 0xfc1f07ff, WR_1|RD_2|LM|SM,        0,              IOCT2,          0,      0 },
+{"law",                        "d,(b),t",      0x7000059f, 0xfc0007ff, WR_1|RD_2|RD_3|LM|SM,   0,              IOCT2,          0,      0 },
+{"lawd",               "d,(b),t",      0x700005df, 0xfc0007ff, WR_1|RD_2|RD_3|LM|SM,   0,              IOCT2,          0,      0 },
+{"lb",                 "t,o(b)",       0x80000000, 0xfc000000, WR_1|RD_3|LM,           0,              I1,             0,      0 },
 {"lb",                 "t,A(b)",       0,    (int) M_LB_AB,    INSN_MACRO,             0,              I1,             0,      0 },
-{"lbu",                        "t,o(b)",       0x90000000, 0xfc000000, WR_1|RD_3|LDD,          0,              I1,             0,      0 },
+{"lbu",                        "t,o(b)",       0x90000000, 0xfc000000, WR_1|RD_3|LM,           0,              I1,             0,      0 },
 {"lbu",                        "t,A(b)",       0,    (int) M_LBU_AB,   INSN_MACRO,             0,              I1,             0,      0 },
-{"lbx",                        "d,t(b)",       0x7c00058a, 0xfc0007ff, WR_1|RD_2|RD_3|LDD,     0,              IOCT2,          0,      0 },
-{"lbux",               "d,t(b)",       0x7c00018a, 0xfc0007ff, WR_1|RD_2|RD_3|LDD,     0,              IOCT2,          D32,    0},
-{"ldx",                        "d,t(b)",       0x7c00020a, 0xfc0007ff, WR_1|RD_2|RD_3|LDD,     0,              IOCT2,          D64,    0},
-{"lhx",                        "d,t(b)",       0x7c00010a, 0xfc0007ff, WR_1|RD_2|RD_3|LDD,     0,              IOCT2,          D32,    0},
-{"lhux",               "d,t(b)",       0x7c00050a, 0xfc0007ff, WR_1|RD_2|RD_3|LDD,     0,              IOCT2,          0,      0 },
-{"lwx",                        "d,t(b)",       0x7c00000a, 0xfc0007ff, WR_1|RD_2|RD_3|LDD,     0,              IOCT2,          D32,    0},
-{"lwux",               "d,t(b)",       0x7c00040a, 0xfc0007ff, WR_1|RD_2|RD_3|LDD,     0,              IOCT2,          0,      0 },
+{"lbx",                        "d,t(b)",       0x7c00058a, 0xfc0007ff, WR_1|RD_2|RD_3|LM,      0,              IOCT2,          0,      0 },
+{"lbux",               "d,t(b)",       0x7c00018a, 0xfc0007ff, WR_1|RD_2|RD_3|LM,      0,              IOCT2,          D32,    0},
+{"ldx",                        "d,t(b)",       0x7c00020a, 0xfc0007ff, WR_1|RD_2|RD_3|LM,      0,              IOCT2,          D64,    0},
+{"lhx",                        "d,t(b)",       0x7c00010a, 0xfc0007ff, WR_1|RD_2|RD_3|LM,      0,              IOCT2,          D32,    0},
+{"lhux",               "d,t(b)",       0x7c00050a, 0xfc0007ff, WR_1|RD_2|RD_3|LM,      0,              IOCT2,          0,      0 },
+{"lwx",                        "d,t(b)",       0x7c00000a, 0xfc0007ff, WR_1|RD_2|RD_3|LM,      0,              IOCT2,          D32,    0},
+{"lwux",               "d,t(b)",       0x7c00040a, 0xfc0007ff, WR_1|RD_2|RD_3|LM,      0,              IOCT2,          0,      0 },
 {"lca",                        "t,A(b)",       0,    (int) M_LCA_AB,   INSN_MACRO,             0,              I1,             0,      0 },
 /* The macro has to be first to handle o32 correctly.  */
 {"ld",                 "t,A(b)",       0,    (int) M_LD_AB,    INSN_MACRO,             0,              I1,             0,      0 },
-{"ld",                 "t,o(b)",       0xdc000000, 0xfc000000, WR_1|RD_3,              0,              I3,             0,      0 },
-{"ldaddw",             "t,b",          0x70000010, 0xfc00ffff, MOD_1|RD_2|SM,          0,              XLR,            0,      0 },
-{"ldaddwu",            "t,b",          0x70000011, 0xfc00ffff, MOD_1|RD_2|SM,          0,              XLR,            0,      0 },
-{"ldaddd",             "t,b",          0x70000012, 0xfc00ffff, MOD_1|RD_2|SM,          0,              XLR,            0,      0 },
+{"ld",                 "t,o(b)",       0xdc000000, 0xfc000000, WR_1|RD_3|LM,           0,              I3,             0,      0 },
+{"ldaddw",             "t,b",          0x70000010, 0xfc00ffff, MOD_1|RD_2|LM|SM,       0,              XLR,            0,      0 },
+{"ldaddwu",            "t,b",          0x70000011, 0xfc00ffff, MOD_1|RD_2|LM|SM,       0,              XLR,            0,      0 },
+{"ldaddd",             "t,b",          0x70000012, 0xfc00ffff, MOD_1|RD_2|LM|SM,       0,              XLR,            0,      0 },
 {"ldc1",               "T,o(b)",       0xd4000000, 0xfc000000, WR_1|RD_3|CLD|FP_D,     0,              I2,             0,      SF },
 {"ldc1",               "E,o(b)",       0xd4000000, 0xfc000000, WR_1|RD_3|CLD|FP_D,     0,              I2,             0,      SF },
 {"ldc1",               "T,A(b)",       0,    (int) M_LDC1_AB,  INSN_MACRO,             INSN2_M_FP_D,   I2,             0,      SF },
@@ -1176,31 +1176,31 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"ldc2",               "E,A(b)",       0,    (int) M_LDC2_AB,  INSN_MACRO,             0,              I2,             0,      IOCT|IOCTP|IOCT2|EE },
 {"ldc3",               "E,o(b)",       0xdc000000, 0xfc000000, RD_3|WR_CC|CLD,         0,              I2,             0,      IOCT|IOCTP|IOCT2|EE },
 {"ldc3",               "E,A(b)",       0,    (int) M_LDC3_AB,  INSN_MACRO,             0,              I2,             0,      IOCT|IOCTP|IOCT2|EE },
-{"ldl",                        "t,o(b)",       0x68000000, 0xfc000000, WR_1|RD_3|LDD,          0,              I3,             0,      0 },
+{"ldl",                        "t,o(b)",       0x68000000, 0xfc000000, WR_1|RD_3|LM,           0,              I3,             0,      0 },
 {"ldl",                        "t,A(b)",       0,    (int) M_LDL_AB,   INSN_MACRO,             0,              I3,             0,      0 },
-{"ldr",                        "t,o(b)",       0x6c000000, 0xfc000000, WR_1|RD_3|LDD,          0,              I3,             0,      0 },
+{"ldr",                        "t,o(b)",       0x6c000000, 0xfc000000, WR_1|RD_3|LM,           0,              I3,             0,      0 },
 {"ldr",                        "t,A(b)",       0,    (int) M_LDR_AB,   INSN_MACRO,             0,              I3,             0,      0 },
-{"ldxc1",              "D,t(b)",       0x4c000001, 0xfc00f83f, WR_1|RD_2|RD_3|LDD|FP_D, 0,             I4_33,          0,      0 },
-{"lh",                 "t,o(b)",       0x84000000, 0xfc000000, WR_1|RD_3|LDD,          0,              I1,             0,      0 },
+{"ldxc1",              "D,t(b)",       0x4c000001, 0xfc00f83f, WR_1|RD_2|RD_3|LM|FP_D, 0,              I4_33,          0,      0 },
+{"lh",                 "t,o(b)",       0x84000000, 0xfc000000, WR_1|RD_3|LM,           0,              I1,             0,      0 },
 {"lh",                 "t,A(b)",       0,    (int) M_LH_AB,    INSN_MACRO,             0,              I1,             0,      0 },
-{"lhu",                        "t,o(b)",       0x94000000, 0xfc000000, WR_1|RD_3|LDD,          0,              I1,             0,      0 },
+{"lhu",                        "t,o(b)",       0x94000000, 0xfc000000, WR_1|RD_3|LM,           0,              I1,             0,      0 },
 {"lhu",                        "t,A(b)",       0,    (int) M_LHU_AB,   INSN_MACRO,             0,              I1,             0,      0 },
 /* li is at the start of the table.  */
 {"li.d",               "t,F",          0,    (int) M_LI_D,     INSN_MACRO,             INSN2_M_FP_D,   I1,             0,      SF },
 {"li.d",               "T,L",          0,    (int) M_LI_DD,    INSN_MACRO,             INSN2_M_FP_D,   I1,             0,      SF },
 {"li.s",               "t,f",          0,    (int) M_LI_S,     INSN_MACRO,             INSN2_M_FP_S,   I1,             0,      0 },
 {"li.s",               "T,l",          0,    (int) M_LI_SS,    INSN_MACRO,             INSN2_M_FP_S,   I1,             0,      0 },
-{"ll",                 "t,o(b)",       0xc0000000, 0xfc000000, WR_1|RD_3|LDD,          0,              I2,             0,      EE },
+{"ll",                 "t,o(b)",       0xc0000000, 0xfc000000, WR_1|RD_3|LM,           0,              I2,             0,      EE },
 {"ll",                 "t,A(b)",       0,    (int) M_LL_AB,    INSN_MACRO,             0,              I2,             0,      EE },
-{"lld",                        "t,o(b)",       0xd0000000, 0xfc000000, WR_1|RD_3|LDD,          0,              I3,             0,      EE },
+{"lld",                        "t,o(b)",       0xd0000000, 0xfc000000, WR_1|RD_3|LM,           0,              I3,             0,      EE },
 {"lld",                        "t,A(b)",       0,    (int) M_LLD_AB,   INSN_MACRO,             0,              I3,             0,      EE },
-{"lq",                 "t,o(b)",       0x78000000, 0xfc000000, WR_1|RD_3,              0,              MMI,            0,      0 },
+{"lq",                 "t,o(b)",       0x78000000, 0xfc000000, WR_1|RD_3|LM,           0,              MMI,            0,      0 },
 {"lq",                 "t,A(b)",       0,    (int) M_LQ_AB,    INSN_MACRO,             0,              MMI,            0,      0 },
-{"lqc2",               "+7,o(b)",      0xd8000000, 0xfc000000, RD_3|WR_C2,             0,              EE,             0,      0 },
+{"lqc2",               "+7,o(b)",      0xd8000000, 0xfc000000, RD_3|WR_C2|LM,          0,              EE,             0,      0 },
 {"lqc2",               "+7,A(b)",      0,    (int) M_LQC2_AB,  INSN_MACRO,             0,              EE,             0,      0 },
 {"lui",                        "t,u",          0x3c000000, 0xffe00000, WR_1,                   0,              I1,             0,      0 },
-{"luxc1",              "D,t(b)",       0x4c000005, 0xfc00f83f, WR_1|RD_2|RD_3|LDD|FP_D, 0,             I5_33|N55,      0,      0},
-{"lw",                 "t,o(b)",       0x8c000000, 0xfc000000, WR_1|RD_3|LDD,          0,              I1,             0,      0 },
+{"luxc1",              "D,t(b)",       0x4c000005, 0xfc00f83f, WR_1|RD_2|RD_3|LM|FP_D, 0,              I5_33|N55,      0,      0},
+{"lw",                 "t,o(b)",       0x8c000000, 0xfc000000, WR_1|RD_3|LM,           0,              I1,             0,      0 },
 {"lw",                 "t,A(b)",       0,    (int) M_LW_AB,    INSN_MACRO,             0,              I1,             0,      0 },
 {"lwc0",               "E,o(b)",       0xc0000000, 0xfc000000, RD_3|WR_CC|CLD,         0,              I1,             0,      IOCT|IOCTP|IOCT2 },
 {"lwc0",               "E,A(b)",       0,    (int) M_LWC0_AB,  INSN_MACRO,             0,              I1,             0,      IOCT|IOCTP|IOCT2 },
@@ -1214,19 +1214,19 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"lwc2",               "E,A(b)",       0,    (int) M_LWC2_AB,  INSN_MACRO,             0,              I1,             0,      IOCT|IOCTP|IOCT2|EE },
 {"lwc3",               "E,o(b)",       0xcc000000, 0xfc000000, RD_3|WR_CC|CLD,         0,              I1,             0,      IOCT|IOCTP|IOCT2|EE },
 {"lwc3",               "E,A(b)",       0,    (int) M_LWC3_AB,  INSN_MACRO,             0,              I1,             0,      IOCT|IOCTP|IOCT2|EE },
-{"lwl",                        "t,o(b)",       0x88000000, 0xfc000000, WR_1|RD_3|LDD,          0,              I1,             0,      0 },
+{"lwl",                        "t,o(b)",       0x88000000, 0xfc000000, WR_1|RD_3|LM,           0,              I1,             0,      0 },
 {"lwl",                        "t,A(b)",       0,    (int) M_LWL_AB,   INSN_MACRO,             0,              I1,             0,      0 },
-{"lcache",             "t,o(b)",       0x88000000, 0xfc000000, WR_1|RD_3|LDD,          0,              I2,             0,      0 }, /* same */
+{"lcache",             "t,o(b)",       0x88000000, 0xfc000000, WR_1|RD_3|LM,           0,              I2,             0,      0 }, /* same */
 {"lcache",             "t,A(b)",       0,    (int) M_LWL_AB,   INSN_MACRO,             0,              I2,             0,      0 }, /* as lwl */
-{"lwr",                        "t,o(b)",       0x98000000, 0xfc000000, WR_1|RD_3|LDD,          0,              I1,             0,      0 },
+{"lwr",                        "t,o(b)",       0x98000000, 0xfc000000, WR_1|RD_3|LM,           0,              I1,             0,      0 },
 {"lwr",                        "t,A(b)",       0,    (int) M_LWR_AB,   INSN_MACRO,             0,              I1,             0,      0 },
-{"flush",              "t,o(b)",       0x98000000, 0xfc000000, WR_1|RD_3|LDD,          0,              I2,             0,      0 }, /* same */
+{"flush",              "t,o(b)",       0x98000000, 0xfc000000, WR_1|RD_3|LM,           0,              I2,             0,      0 }, /* same */
 {"flush",              "t,A(b)",       0,    (int) M_LWR_AB,   INSN_MACRO,             0,              I2,             0,      0 }, /* as lwr */
 {"fork",               "d,s,t",        0x7c000008, 0xfc0007ff, WR_1|RD_2|RD_3|TRAP,    0,              0,              MT32,   0 },
-{"lwu",                        "t,o(b)",       0x9c000000, 0xfc000000, WR_1|RD_3|LDD,          0,              I3,             0,      0 },
+{"lwu",                        "t,o(b)",       0x9c000000, 0xfc000000, WR_1|RD_3|LM,           0,              I3,             0,      0 },
 {"lwu",                        "t,A(b)",       0,    (int) M_LWU_AB,   INSN_MACRO,             0,              I3,             0,      0 },
-{"lwxc1",              "D,t(b)",       0x4c000000, 0xfc00f83f, WR_1|RD_2|RD_3|LDD|FP_S,     0,         I4_33,          0,      0 },
-{"lwxs",               "d,t(b)",       0x70000088, 0xfc0007ff, WR_1|RD_2|RD_3|LDD,          0,         0,              SMT,    0 },
+{"lwxc1",              "D,t(b)",       0x4c000000, 0xfc00f83f, WR_1|RD_2|RD_3|LM|FP_S,     0,          I4_33,          0,      0 },
+{"lwxs",               "d,t(b)",       0x70000088, 0xfc0007ff, WR_1|RD_2|RD_3|LM,           0,         0,              SMT,    0 },
 {"macc",               "d,s,t",        0x00000028, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO,      0,         N412,           0,      0 },
 {"macc",               "d,s,t",        0x00000158, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO,      0,         N5,             0,      0 },
 {"maccs",              "d,s,t",        0x00000428, 0xfc0007ff, WR_1|RD_2|RD_3|WR_HILO,      0,         N412,           0,      0 },
@@ -1831,9 +1831,9 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"suxc1",              "S,t(b)",       0x4c00000d, 0xfc0007ff, RD_1|RD_2|RD_3|SM|FP_D, 0,              I5_33|N55,      0,      0},
 {"sw",                 "t,o(b)",       0xac000000, 0xfc000000, RD_1|RD_3|SM,           0,              I1,             0,      0 },
 {"sw",                 "t,A(b)",       0,    (int) M_SW_AB,    INSN_MACRO,             0,              I1,             0,      0 },
-{"swapw",              "t,b",          0x70000014, 0xfc00ffff, MOD_1|RD_2|SM,          0,              XLR,            0,      0 },
-{"swapwu",             "t,b",          0x70000015, 0xfc00ffff, MOD_1|RD_2|SM,          0,              XLR,            0,      0 },
-{"swapd",              "t,b",          0x70000016, 0xfc00ffff, MOD_1|RD_2|SM,          0,              XLR,            0,      0 },
+{"swapw",              "t,b",          0x70000014, 0xfc00ffff, MOD_1|RD_2|LM|SM,       0,              XLR,            0,      0 },
+{"swapwu",             "t,b",          0x70000015, 0xfc00ffff, MOD_1|RD_2|LM|SM,       0,              XLR,            0,      0 },
+{"swapd",              "t,b",          0x70000016, 0xfc00ffff, MOD_1|RD_2|LM|SM,       0,              XLR,            0,      0 },
 {"swc0",               "E,o(b)",       0xe0000000, 0xfc000000, RD_3|RD_C0|SM,          0,              I1,             0,      IOCT|IOCTP|IOCT2 },
 {"swc0",               "E,A(b)",       0,    (int) M_SWC0_AB,  INSN_MACRO,             0,              I1,             0,      IOCT|IOCTP|IOCT2 },
 {"swc1",               "T,o(b)",       0xe4000000, 0xfc000000, RD_1|RD_3|SM|FP_S,      0,              I1,             0,      0 },
@@ -2538,21 +2538,21 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"sequ",               "S,T",          0x46800032, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D,   0,              IL2E,           0,      0 },
 {"sequ",               "S,T",          0x4b80000c, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D,   0,              IL2F|IL3A,      0,      0 },
 /* MIPS Enhanced VA Scheme */
-{"lbue",               "t,+j(b)",      0x7c000028, 0xfc00007f, WR_1|RD_3|LDD,          0,              0,              EVA,    0 },
+{"lbue",               "t,+j(b)",      0x7c000028, 0xfc00007f, WR_1|RD_3|LM,           0,              0,              EVA,    0 },
 {"lbue",               "t,A(b)",       0,    (int) M_LBUE_AB,  INSN_MACRO,             0,              0,              EVA,    0 },
-{"lhue",               "t,+j(b)",      0x7c000029, 0xfc00007f, WR_1|RD_3|LDD,          0,              0,              EVA,    0 },
+{"lhue",               "t,+j(b)",      0x7c000029, 0xfc00007f, WR_1|RD_3|LM,           0,              0,              EVA,    0 },
 {"lhue",               "t,A(b)",       0,    (int) M_LHUE_AB,  INSN_MACRO,             0,              0,              EVA,    0 },
-{"lbe",                        "t,+j(b)",      0x7c00002c, 0xfc00007f, WR_1|RD_3|LDD,          0,              0,              EVA,    0 },
+{"lbe",                        "t,+j(b)",      0x7c00002c, 0xfc00007f, WR_1|RD_3|LM,           0,              0,              EVA,    0 },
 {"lbe",                        "t,A(b)",       0,    (int) M_LBE_AB,   INSN_MACRO,             0,              0,              EVA,    0 },
-{"lhe",                        "t,+j(b)",      0x7c00002d, 0xfc00007f, WR_1|RD_3|LDD,          0,              0,              EVA,    0 },
+{"lhe",                        "t,+j(b)",      0x7c00002d, 0xfc00007f, WR_1|RD_3|LM,           0,              0,              EVA,    0 },
 {"lhe",                        "t,A(b)",       0,    (int) M_LHE_AB,   INSN_MACRO,             0,              0,              EVA,    0 },
-{"lle",                        "t,+j(b)",      0x7c00002e, 0xfc00007f, WR_1|RD_3|LDD,          0,              0,              EVA,    0 },
+{"lle",                        "t,+j(b)",      0x7c00002e, 0xfc00007f, WR_1|RD_3|LM,           0,              0,              EVA,    0 },
 {"lle",                        "t,A(b)",       0,    (int) M_LLE_AB,   INSN_MACRO,             0,              0,              EVA,    0 },
-{"lwe",                        "t,+j(b)",      0x7c00002f, 0xfc00007f, WR_1|RD_3|LDD,          0,              0,              EVA,    0 },
+{"lwe",                        "t,+j(b)",      0x7c00002f, 0xfc00007f, WR_1|RD_3|LM,           0,              0,              EVA,    0 },
 {"lwe",                        "t,A(b)",       0,    (int) M_LWE_AB,   INSN_MACRO,             0,              0,              EVA,    0 },
-{"lwle",               "t,+j(b)",      0x7c000019, 0xfc00007f, WR_1|RD_3|LDD,          0,              0,              EVA,    0 },
+{"lwle",               "t,+j(b)",      0x7c000019, 0xfc00007f, WR_1|RD_3|LM,           0,              0,              EVA,    0 },
 {"lwle",               "t,A(b)",       0,    (int) M_LWLE_AB,  INSN_MACRO,             0,              0,              EVA,    0 },
-{"lwre",               "t,+j(b)",      0x7c00001a, 0xfc00007f, WR_1|RD_3|LDD,          0,              0,              EVA,    0 },
+{"lwre",               "t,+j(b)",      0x7c00001a, 0xfc00007f, WR_1|RD_3|LM,           0,              0,              EVA,    0 },
 {"lwre",               "t,A(b)",       0,    (int) M_LWRE_AB,  INSN_MACRO,             0,              0,              EVA,    0 },
 {"sbe",                        "t,+j(b)",      0x7c00001c, 0xfc00007f, RD_1|RD_3|SM,           0,              0,              EVA,    0 },
 {"sbe",                        "t,A(b)",       0,    (int) M_SBE_AB,   INSN_MACRO,             0,              0,              EVA,    0 },
@@ -2731,10 +2731,10 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"clei_u.h",           "+d,+e,+$",     0x7aa00007, 0xffe0003f, WR_1|RD_2,              0,              0,              MSA,    0 },
 {"clei_u.w",           "+d,+e,+$",     0x7ac00007, 0xffe0003f, WR_1|RD_2,              0,              0,              MSA,    0 },
 {"clei_u.d",           "+d,+e,+$",     0x7ae00007, 0xffe0003f, WR_1|RD_2,              0,              0,              MSA,    0 },
-{"ld.b",               "+d,+T(d)",     0x78000020, 0xfc00003f, WR_1|RD_3|LDD,          0,              0,              MSA,    0 },
-{"ld.h",               "+d,+U(d)",     0x78000021, 0xfc00003f, WR_1|RD_3|LDD,          0,              0,              MSA,    0 },
-{"ld.w",               "+d,+V(d)",     0x78000022, 0xfc00003f, WR_1|RD_3|LDD,          0,              0,              MSA,    0 },
-{"ld.d",               "+d,+W(d)",     0x78000023, 0xfc00003f, WR_1|RD_3|LDD,          0,              0,              MSA,    0 },
+{"ld.b",               "+d,+T(d)",     0x78000020, 0xfc00003f, WR_1|RD_3|LM,           0,              0,              MSA,    0 },
+{"ld.h",               "+d,+U(d)",     0x78000021, 0xfc00003f, WR_1|RD_3|LM,           0,              0,              MSA,    0 },
+{"ld.w",               "+d,+V(d)",     0x78000022, 0xfc00003f, WR_1|RD_3|LM,           0,              0,              MSA,    0 },
+{"ld.d",               "+d,+W(d)",     0x78000023, 0xfc00003f, WR_1|RD_3|LM,           0,              0,              MSA,    0 },
 {"st.b",               "+d,+T(d)",     0x78000024, 0xfc00003f, RD_1|RD_3|SM,           0,              0,              MSA,    0 },
 {"st.h",               "+d,+U(d)",     0x78000025, 0xfc00003f, RD_1|RD_3|SM,           0,              0,              MSA,    0 },
 {"st.w",               "+d,+V(d)",     0x78000026, 0xfc00003f, RD_1|RD_3|SM,           0,              0,              MSA,    0 },