Even more instruction tests

diff --git a/sim/testsuite/ChangeLog b/sim/testsuite/ChangeLog
index 52ff74c24b32fa015f25365fc238da01826c7a52..71a5158cc28e44f2a6d6be3b8067505cd032a392 100644 (file)
--- a/sim/testsuite/ChangeLog
+++ b/sim/testsuite/ChangeLog
@@ -1,5 +1,16 @@
 Thu Feb 19 11:15:45 1998  Nick Clifton  <nickc@cygnus.com>
 
+       * sim/m32r/bl24.cgs: Test long BL instruction.
+       * sim/m32r/bl8.cgs: Test short BL instruction.
+       * sim/m32r/blez.cgs: Test BLEZ instruction.
+       * sim/m32r/bltz.cgs: Test BLTZ instruction.
+       * sim/m32r/bne.cgs: Test BNE instruction.
+       * sim/m32r/bnez.cgs: Test BNEZ instruction.
+       * sim/m32r/bra24.cgs: Test long BRA instruction.
+       * sim/m32r/bra8.cgs: Test short BRA instruction.
+       * sim/m32r/jl.cgs: Test JL instruction.
+       * sim/m32r/or.cgs: Test OR instruction.
+       * sim/m32r/jmp.cgs: Test JMP instruction.
        * sim/m32r/and.cgs: Test AND instruction.
        * sim/m32r/and3.cgs: Test AND3 instruction.
        * sim/m32r/beq.cgs: Test BEQ instruction.
@@ -11,17 +22,11 @@ Thu Feb 19 11:15:45 1998  Nick Clifton  <nickc@cygnus.com>
        * sim/m32r/cmpu.cgs: Test CMPU instruction.
        * sim/m32r/cmpui.cgs: Test CMPUI instruction.
        * sim/m32r/div.cgs: Test DIV instruction.
-       * sim/m32r/divh.cgs: Test DIVH instruction.
-
-       * sim/m32r/bcl8.cgs: Test short BCL instruction.
-       * sim/m32r/bncl24.cgs: Test long BNCL instruction.
-       * sim/m32r/bncl8.cgs: Test short BNCL instruction.
+       * sim/m32r/divu.cgs: Test DIVU instruction.
        * sim/m32r/cmpeq.cgs: Test CMPEQ instruction.
-       * sim/m32r/cmpz.cgs: Test CMPZ instruction.
        * sim/m32r/sll.cgs: Test SLL instruction.
        * sim/m32r/sll3.cgs: Test SLL3 instruction.
        * sim/m32r/slli.cgs: Test SLLI instruction.
-       * sim/m32r/bcl24.cgs: Test long version of BCL instruction
        * sim/m32r/sra.cgs: Test SRA instruction.
        * sim/m32r/sra3.cgs: Test SRA3 instruction.
        * sim/m32r/srai.cgs: Test SRAI instruction.
@@ -30,7 +35,16 @@ Thu Feb 19 11:15:45 1998  Nick Clifton  <nickc@cygnus.com>
        * sim/m32r/srli.cgs: Test SRLI instruction.
        * sim/m32r/xor3.cgs: Test XOR3 instruction.
        * sim/m32r/xor.cgs: Test XOR instruction.
-
+start-sanitize-m342rx  
+       * sim/m32r/jnc.cgs: Test JNC instruction.
+       * sim/m32r/jc.cgs: Test JC instruction.
+       * sim/m32r/cmpz.cgs: Test CMPZ instruction.
+       * sim/m32r/bcl24.cgs: Test long version of BCL instruction
+       * sim/m32r/bcl8.cgs: Test short BCL instruction.
+       * sim/m32r/bncl24.cgs: Test long BNCL instruction.
+       * sim/m32r/bncl8.cgs: Test short BNCL instruction.
+       * sim/m32r/divh.cgs: Test DIVH instruction.
+end-sanitize-m342rx    
 Tue Feb 17 12:46:05 1998  Doug Evans  <devans@seba.cygnus.com>
 
        * config/default.exp: New file.

diff --git a/sim/testsuite/sim/m32r/bl24.cgs b/sim/testsuite/sim/m32r/bl24.cgs
new file mode 100644 (file)
index 0000000..f4ebcd3
--- /dev/null
+++ b/sim/testsuite/sim/m32r/bl24.cgs
@@ -0,0 +1,19 @@
+# m32r testcase for bl $disp24
+# mach(): m32r m32rx
+
+       .include "testutils.inc"
+
+       start
+
+       .global bl24
+bl24:
+       bl.l test0pass
+test1fail:
+       fail
+
+test0pass:
+       seth r4, high (test1fail)
+       or3  r4, r4, low (test1fail)
+       bne  r4, r14, test1fail
+
+       pass

diff --git a/sim/testsuite/sim/m32r/bl8.cgs b/sim/testsuite/sim/m32r/bl8.cgs
new file mode 100644 (file)
index 0000000..ad2a649
--- /dev/null
+++ b/sim/testsuite/sim/m32r/bl8.cgs
@@ -0,0 +1,19 @@
+# m32r testcase for bl $disp8
+# mach(): m32r m32rx
+
+       .include "testutils.inc"
+
+       start
+
+       .global bl8
+bl8:
+       bl.s test0pass
+test1fail:
+       fail
+
+test0pass:
+       seth r4, high (test1fail)
+       or3  r4, r4, low (test1fail)
+       bne  r4, r14, test1fail
+
+       pass

diff --git a/sim/testsuite/sim/m32r/jl.cgs b/sim/testsuite/sim/m32r/jl.cgs
new file mode 100644 (file)
index 0000000..649a004
--- /dev/null
+++ b/sim/testsuite/sim/m32r/jl.cgs
@@ -0,0 +1,20 @@
+# m32r testcase for jl $sr
+# mach(): m32r m32rx
+
+       .include "testutils.inc"
+
+       start
+
+       .global jl
+jl:
+       seth r4, high (ok)
+       or3  r4, r4, low (ok)
+       jl   r4
+not_ok:
+       fail
+ok:
+       seth r4, high (not_ok)
+       or3  r4, r4, low (not_ok)
+       bne  r4, r14, not_ok
+
+       pass

diff --git a/sim/testsuite/sim/m32r/jmp.cgs b/sim/testsuite/sim/m32r/jmp.cgs
new file mode 100644 (file)
index 0000000..717a455
--- /dev/null
+++ b/sim/testsuite/sim/m32r/jmp.cgs
@@ -0,0 +1,16 @@
+# m32r testcase for jmp $sr
+# mach(): m32r m32rx
+
+       .include "testutils.inc"
+
+       start
+
+       .global jmp
+jmp:
+       seth r4, high (ok)
+       or3  r4, r4, low (ok)
+       jmp  r4
+
+       fail
+ok:
+       pass