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diff --git a/openpower/sv/overview.mdwn b/openpower/sv/overview.mdwn
index ad40ed02f2844f7d0381d8deca78751be49cc2b7..7ee70802cd8dd2a461d5282d5ec6668491b08fe9 100644 (file)
--- a/openpower/sv/overview.mdwn
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@@ -9,7 +9,7 @@ a seductive simplicity that is easy to implement in hardware.  Even with predica
 
 Cray-style variable-length Vectors on the other hand result in stunningly elegant and small loops, with no alarmingly high setup and cleanup code, where at the hardware level the microarchitecture may execute from one element right the way through to tens of thousands at a time, yet the executable remains exactly the same and the ISA remains clear, true to the RISC paradigm, and clean.  Unlike in SIMD, powers of two limitations are not involved in either the hardware nor in the assembly code.
 
-SimpleV takes the Cray style Vector principle and applies it to a Scalar ISA, in the process allowing register file size increases using "tagging" (similar to how x86 originally extended registers from 32 to 64 bit).
+SimpleV takes the Cray style Vector principle and applies it in the abstract to a Scalar ISA, in the process allowing register file size increases using "tagging" (similar to how x86 originally extended registers from 32 to 64 bit).
 
 The fundamentals are: