Re: [libre-riscv-dev] cache SRAM organisation

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+From: Staf Verhaegen <staf@fibraservi.eu>
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+Date: Fri, 27 Mar 2020 11:36:15 +0100
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+Subject: Re: [libre-riscv-dev] cache SRAM organisation
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+Luke Kenneth Casson Leighton schreef op vr 27-03-2020 om 09:44 [+0000]:
+> On Fri, Mar 27, 2020 at 9:25 AM Staf Verhaegen <staf@fibraservi.eu> wrote=
+:
+> > My point is that you will have the same performance for the fixed 5-sta=
+ge pipeline running @ 800MHz
+>=20
+> no, it won't: it'll be half the clock speed.  it won't be double thenumbe=
+r of computations: it'll be the exact same number ofcomputations.  therefor=
+e, half the speed means half the number ofcomputations because the *through=
+put* is the same
+> when you use "cpufreq-set" to change the clock rate, if the clock rateis =
+halved, the computer is twice as slow.
+
+You are right.
+
+> yes it's confusing :)
+
+Yes and no, it is the basic functionality of a pipeline :(
+You have the same latency but can have double the number of operations in f=
+light.
+
+greets,
+Staf.
+
+
+
+
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+--===============8086656049151897504==
+Content-Type: text/plain; charset="utf-8"
+MIME-Version: 1.0
+Content-Transfer-Encoding: base64
+Content-Disposition: inline
+
+X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KbGlicmUtcmlz
+Y3YtZGV2IG1haWxpbmcgbGlzdApsaWJyZS1yaXNjdi1kZXZAbGlzdHMubGlicmUtcmlzY3Yub3Jn
+Cmh0dHA6Ly9saXN0cy5saWJyZS1yaXNjdi5vcmcvbWFpbG1hbi9saXN0aW5mby9saWJyZS1yaXNj
+di1kZXYK
+
+--===============8086656049151897504==--
+
+
+