add missing reset-HI values to cas_n, cs_n, we_n and act_n

diff --git a/gram/phy/dfi.py b/gram/phy/dfi.py
index d76b764e9f39cccd3de6b11fc8d297c982312a3c..814ad1bfa7e16af413c95696666e73e9c5cb132b 100644 (file)
--- a/gram/phy/dfi.py
+++ b/gram/phy/dfi.py
@@ -43,6 +43,11 @@ class Interface:
                                          nranks, databits),
                        name=name)
             self.phases += [p]
+            # set all logic-inverted x_n signal resets to on at power-up
+            p.cas.reset = 1
+            p.cs_n.reset = -1
+            p.we.reset = 1
+            p.act.reset = 1
 
     def connect(self, target):
         if not isinstance(target, Interface):