abc9: use (* abc9_keep *) instead of (* abc9_scc *); apply to $_DFF_?_

instead of moving them to $__ prefix

diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc
index 3aa0e11101f2b2f52def9d815026fd06a824acd0..69797ceaf693f8fd05c34d45a62b4839e8f60400 100644 (file)
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@ -177,12 +177,12 @@ struct XAigerWriter
                                undriven_bits.insert(bit);
                                unused_bits.insert(bit);
 
-                               bool scc = wire->attributes.count(ID::abc9_scc);
-                               if (wire->port_input || scc)
+                               bool keep = wire->get_bool_attribute(ID::abc9_keep);
+                               if (wire->port_input || keep)
                                        input_bits.insert(bit);
 
-                               bool keep = wire->get_bool_attribute(ID::keep);
-                               if (wire->port_output || keep || scc) {
+                               keep = keep || wire->get_bool_attribute(ID::keep);
+                               if (wire->port_output || keep) {
                                        if (bit != wirebit)
                                                alias_map[wirebit] = bit;
                                        output_bits.insert(wirebit);
@@ -225,7 +225,7 @@ struct XAigerWriter
                                        continue;
                                }
 
-                               if (dff_mode && cell->type.in(ID($_DFF_N_), ID($_DFF_P_)))
+                               if (dff_mode && cell->type.in(ID($_DFF_N_), ID($_DFF_P_)) && !cell->get_bool_attribute(ID::abc9_keep))
                                {
                                        SigBit D = sigmap(cell->getPort(ID::D).as_bit());
                                        SigBit Q = sigmap(cell->getPort(ID::Q).as_bit());

diff --git a/kernel/constids.inc b/kernel/constids.inc
index 25996d2d863175f52aeda0570b0cc2dae2566229..345bfaee87dcba12776208855ae82ef26d7d51d2 100644 (file)
--- a/kernel/constids.inc
+++ b/kernel/constids.inc
@@ -5,9 +5,9 @@ X(abc9_box_seq)
 X(abc9_bypass)
 X(abc9_carry)
 X(abc9_flop)
+X(abc9_keep)
 X(abc9_lut)
 X(abc9_mergeability)
-X(abc9_scc)
 X(abc9_scc_id)
 X(abcgroup)
 X(ABITS)

diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc
index 6a8dbde8baf3d3aca7a9b19e6a6c30163d3c57c6..10c980f733da8ff0d334b6adb1440b0f0726c690 100644 (file)
--- a/passes/techmap/abc9_ops.cc
+++ b/passes/techmap/abc9_ops.cc
@@ -563,7 +563,7 @@ void mark_scc(RTLIL::Module *module)
                        if (c.second.is_fully_const()) continue;
                        if (cell->output(c.first)) {
                                Wire *w = module->addWire(NEW_ID, GetSize(c.second));
-                               w->set_bool_attribute(ID::abc9_scc);
+                               w->set_bool_attribute(ID::abc9_keep);
                                module->connect(w, c.second);
                                c.second = w;
                        }
@@ -1154,7 +1154,7 @@ void reintegrate(RTLIL::Module *module, bool dff_mode)
 
                // Short out $_DFF_[NP]_ cells since the flop box already has
                //   all the information we need to reconstruct cell
-               if (dff_mode && cell->type.in(ID($_DFF_N_), ID($_DFF_P_))) {
+               if (dff_mode && cell->type.in(ID($_DFF_N_), ID($_DFF_P_)) && !cell->get_bool_attribute(ID::abc9_keep)) {
                        module->connect(cell->getPort(ID::Q), cell->getPort(ID::D));
                        module->remove(cell);
                }
@@ -1373,7 +1373,7 @@ void reintegrate(RTLIL::Module *module, bool dff_mode)
                RTLIL::Wire *mapped_wire = mapped_mod->wire(port);
                RTLIL::Wire *wire = module->wire(port);
                log_assert(wire);
-               wire->attributes.erase(ID::abc9_scc);
+               wire->attributes.erase(ID::abc9_keep);
 
                RTLIL::Wire *remap_wire = module->wire(remap_name(port));
                RTLIL::SigSpec signal(wire, remap_wire->start_offset-wire->start_offset, GetSize(remap_wire));

diff --git a/techlibs/common/abc9_map.v b/techlibs/common/abc9_map.v
index bb2b4a4b188431554eb3112684fb58ed15c57d2d..6ed90b5f5710a5c73c565eddc427765e825d0f09 100644 (file)
--- a/techlibs/common/abc9_map.v
+++ b/techlibs/common/abc9_map.v
@@ -10,7 +10,7 @@ module $_DFF_x_(input C, D, output Q);
       $_DFF_N_ ff (.C(C), .D(D_), .Q(Q));
     end
     else
-      $__DFF_N_ _TECHMAP_REPLACE_ (.C(C), .D(D), .Q(Q)); // hide from abc9 using $__ prefix
+      (* abc9_keep *) $_DFF_N_ _TECHMAP_REPLACE_ (.C(C), .D(D), .Q(Q));
   end
   else if (_TECHMAP_CELLTYPE_ == "$_DFF_P_") begin
     if (_TECHMAP_WIREINIT_Q_ === 1'b0) begin
@@ -18,7 +18,7 @@ module $_DFF_x_(input C, D, output Q);
       $_DFF_P_ ff (.C(C), .D(D_), .Q(Q));
     end
     else
-      $__DFF_P_ _TECHMAP_REPLACE_ (.C(C), .D(D), .Q(Q)); // hide from abc9 using $__ prefix
+      (* abc9_keep *) $_DFF_P_ _TECHMAP_REPLACE_ (.C(C), .D(D), .Q(Q));
   end
   else if (_TECHMAP_CELLTYPE_ != "")
     $error("Unrecognised _TECHMAP_CELLTYPE_");

diff --git a/techlibs/common/abc9_unmap.v b/techlibs/common/abc9_unmap.v
index b765356d8c556902547cd0a346f5358f2717dd95..bcbe914779365a9322a3cebd6e32ddbd1f0e3d92 100644 (file)
--- a/techlibs/common/abc9_unmap.v
+++ b/techlibs/common/abc9_unmap.v
@@ -9,15 +9,3 @@ module $__DFF_x__$abc9_flop (input C, D, Q, output n1);
     $error("Unrecognised _TECHMAP_CELLTYPE_");
   endgenerate
 endmodule
-
-(* techmap_celltype = "$__DFF_N_ $__DFF_P_" *)
-module $__DFF_x_ (input C, D, output Q);
-  parameter _TECHMAP_CELLTYPE_ = "";
-  generate if (_TECHMAP_CELLTYPE_ == "$__DFF_N_")
-    $_DFF_N_ _TECHMAP_REPLACE_ (.C(C), .D(D), .Q(Q));
-  else if (_TECHMAP_CELLTYPE_ == "$__DFF_P_")
-    $_DFF_P_ _TECHMAP_REPLACE_ (.C(C), .D(D), .Q(Q));
-  else if (_TECHMAP_CELLTYPE_ != "")
-    $error("Unrecognised _TECHMAP_CELLTYPE_");
-  endgenerate
-endmodule