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diff --git a/simple_v_extension/sv_prefix_proposal/discussion.rst b/simple_v_extension/sv_prefix_proposal/discussion.rst
index d191b86bd6720a87b01e0a784af614e6c0e87cd7..b9b0b22f6f78b01adffcfd068ea4df6caab687db 100644 (file)
--- a/simple_v_extension/sv_prefix_proposal/discussion.rst
+++ b/simple_v_extension/sv_prefix_proposal/discussion.rst
@@ -12,27 +12,62 @@ Taking an entire major 32 bit opcode (or two) seems logical (RV128 space). I typ
 Or, just "to hell with it" and just take the entire opcode and stuff C into it, no regard for R/I/U/S and instead do whatever we like.
 
 
-+----------+------+---------------------+---------------------+-------+
-| 15 14 13 |  12  |   11 10 9     8   7 | 6    5    4   3   2 | 1   0 |
-+----------+------+---------------------+---------------------+-------+
-|    funct4       |     rd/rs1          |      rs2            | op    |
-+----------+------+---------------------+---------------------+-------+
-|funct3    | imm  |     rd/rs1          |     imm             | op    |
-+----------+------+---------------------+---------------------+-------+
-|funct3    |          imm               |      rs2            | op    |
-+----------+----------------------------+---------+-----------+-------+
-|funct3    |              imm                     |  rd'      | op    |
-+----------+----------------+-----------+---------+-----------+-------+
-|funct3    |    imm         | rs1'      | imm     |  rd'      | op    |
-+----------+----------------+-----------+---------+-----------+-------+
-|funct3    |    imm         | rs1'      | imm     |  rs2'     | op    |
-+----------+----------------+-----------+---------+-----------+-------+
-|       funct6              | rd'/rs1'  | funct2  |  rs2'     | op    |
-+----------+----------------+-----------+---------+-----------+-------+
-|funct3    |   offset       |  rs1'     |     offset          | op    |
-+----------+----------------+-----------+---------------------+-------+
-|funct3    |                jump target                       | op    |
-+----------+--------------------------------------------------+-------+
++----------+------+---------------------+---------------------+-------+--------+
+| 15 14 13 |  12  |   11 10 9     8   7 | 6    5    4   3   2 | 1   0 | format |
++----------+------+---------------------+---------------------+-------+--------+
+|    funct4       |     rd/rs1          |      rs2            | op    | CR     |
++----------+------+---------------------+---------------------+-------+--------+
+|funct3    | imm  |     rd/rs1          |     imm             | op    | CI     |
++----------+------+---------------------+---------------------+-------+--------+
+|funct3    |          imm               |      rs2            | op    | CSS    |
++----------+----------------------------+---------+-----------+-------+--------+
+|funct3    |              imm                     |  rd'      | op    | CIW    |
++----------+----------------+-----------+---------+-----------+-------+--------+
+|funct3    |    imm         | rs1'      | imm     |  rd'      | op    | CL     |
++----------+----------------+-----------+---------+-----------+-------+--------+
+|funct3    |    imm         | rs1'      | imm     |  rs2'     | op    | CS     |
++----------+----------------+-----------+---------+-----------+-------+--------+
+|       funct6              | rd'/rs1'  | funct2  |  rs2'     | op    | CA     |
++----------+----------------+-----------+---------+-----------+-------+--------+
+|funct3    |   offset       |  rs1'     |     offset          | op    | CB     |
++----------+----------------+-----------+---------------------+-------+--------+
+|funct3    |                jump target                       | op    | CJ     |
++----------+--------------------------------------------------+-------+--------+
+
+* 16 bits RVC to go into RV128 "MAJOR OPCODE 2" and "MAJOR OPCODE 3".
+  RVC op[1:0], bit[1] selects OPCODE-2 or OPCODE-3, therefore
+  17 bits remain in the 32-bit opcode space
+* 32-bit opcode prefix takes 7 bits, therefore 10 bits remain to fit
+  a SVPrefix.
+* compared to P48, 11 bits are needed.
+* however, with the exception of LD/ST these all provide *three* operands:
+  rs1, rs2 and rs3.
+* therefore, 1 field can go, and that just leaves what to do with LD/ST
+* should twin-predication be sacrificed?
+* should one of the vectorisation modes be sacrificed?
+* is there room in ohe of the other "MAJOR CUSTOM OPCODEs" (0,1) to
+  fit the "other" mode somehow?
+* can one of the vew bits be sacrificed instead, reducing vitp7 by 1 bit?
+
++---------------+--------+--------+----------+-----+--------+-------------+------+--------+--------+
+| Encoding      | 17     | 16     | 15       | 14  | 13     | 12          | 11:7 | 6      | 5:0    |
++---------------+--------+--------+----------+-----+--------+-------------+------+--------+--------+
+| P32C-LD-type  | rd[5]  | rs1[5] | vitp7[6] | vd  | vs1    | vitp7[5:0]         | *Rsvd* | 011111 |
++---------------+--------+--------+----------+-----+--------+-------------+------+--------+--------+
+| P32C-ST-type  |vitp7[6]| rs1[5] | rs2[5]   | vs2 | vs1    | vitp7[5:0]         | *Rsvd* | 011111 |
++---------------+--------+--------+----------+-----+--------+-------------+------+--------+--------+
+| P32C-R-type   | rd[5]  | rs1[5] | rs2[5]   | vs2 | vs1    | vitp6              | *Rsvd* | 011111 |
++---------------+--------+--------+----------+-----+--------+--------------------+--------+--------+
+| P32C-I-type   | rd[5]  | rs1[5] | vitp7[6] | vd  | vs1    | vitp7[5:0]         | *Rsvd* | 011111 |
++---------------+--------+--------+----------+-----+--------+--------------------+--------+--------+
+| P32C-U-type   | rd[5]  | *Rsvd* | *Rsvd*   | vd  | *Rsvd* | vitp6              | *Rsvd* | 011111 |
++---------------+--------+--------+----------+-----+--------+-------------+------+--------+--------+
+| P32C-FR-type  | rd[5]  | rs1[5] | rs2[5]   | vs2 | vs1    | *Rsvd*      | vtp5 | *Rsvd* | 011111 |
++---------------+--------+--------+----------+-----+--------+-------------+------+--------+--------+
+| P32C-FI-type  | rd[5]  | rs1[5] | vitp7[6] | vd  | vs1    | vitp7[5:0]         | *Rsvd* | 011111 |
++---------------+--------+--------+----------+-----+--------+-------------+------+--------+--------+
+| P32C-FR4-type | rd[5]  | rs1[5] | rs2[5]   | vs2 | rs3[5] | vs3 [#fr4]_ | vtp5 | *Rsvd* | 011111 |
++---------------+--------+--------+----------+-----+--------+-------------+------+--------+--------+
 
 Questions
 =========