re PR target/29756 (SSE intrinsics hard to use without redundant temporaries appearing)

	PR tree-optimization/29756
	gcc.dg/tree-ssa/vector-6.c: Add -Wno-psabi -w to dg-options.
	Add -msse2 for x86 and -maltivec for powerpc.  Use scan-tree-dump-times
	only on selected targets where V4SImode vectors are known to be
	supported.

From-SVN: r236505

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index ce47e644ca0fb1e8010c6f54909a24cfa216473c..94080ab6921a0d19dc2f0d2f9a76c26a5c61d6bf 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,11 @@
+2016-05-20  Jakub Jelinek  <jakub@redhat.com>
+
+       PR tree-optimization/29756
+       gcc.dg/tree-ssa/vector-6.c: Add -Wno-psabi -w to dg-options.
+       Add -msse2 for x86 and -maltivec for powerpc.  Use scan-tree-dump-times
+       only on selected targets where V4SImode vectors are known to be
+       supported.
+
 2016-05-20  Marc Glisse  <marc.glisse@inria.fr>
 
        PR tree-optimization/71079

diff --git a/gcc/testsuite/gcc.dg/tree-ssa/vector-6.c b/gcc/testsuite/gcc.dg/tree-ssa/vector-6.c
index 059ef4ec98c74fb89105c30b08c1efb469f5b959..785e5dfe424c755e511857b8ddc3bfb46d50fa8c 100644 (file)
--- a/gcc/testsuite/gcc.dg/tree-ssa/vector-6.c
+++ b/gcc/testsuite/gcc.dg/tree-ssa/vector-6.c
@@ -1,5 +1,7 @@
 /* { dg-do compile } */
-/* { dg-options "-O -fdump-tree-ccp1" } */
+/* { dg-options "-O -fdump-tree-ccp1 -Wno-psabi -w" } */
+/* { dg-additional-options "-msse2" { target i?86-*-* x86_64-*-* } } */
+/* { dg-additional-options "-maltivec" { target powerpc_altivec_ok } } */
 
 typedef int v4si __attribute__((vector_size (4 * sizeof (int))));
 
@@ -30,4 +32,4 @@ v4si test4 (v4si v, int i)
   return v;
 }
 
-/* { dg-final { scan-tree-dump-times "Now a gimple register: v" 4 "ccp1" } } */
+/* { dg-final { scan-tree-dump-times "Now a gimple register: v" 4 "ccp1" { target { { i?86-*-* x86_64-*-* aarch64*-*-* spu*-*-* } || { powerpc_altivec_ok } } } } } */