hsail: Fix disassembly of load instruction with 3 destination operands

diff --git a/src/arch/hsail/insts/mem_impl.hh b/src/arch/hsail/insts/mem_impl.hh
index 3042e2201b941656fcff341c0bc374c4c35bb3a7..e3529f914bc17f38a245126cda841b1257a0ce62 100644 (file)
--- a/src/arch/hsail/insts/mem_impl.hh
+++ b/src/arch/hsail/insts/mem_impl.hh
@@ -93,6 +93,15 @@ namespace HsailISA
                                          this->dest_vect[1].disassemble(),
                                          this->addr.disassemble());
             break;
+          case 3:
+            this->disassembly = csprintf("%s_%s_%s (%s,%s,%s), %s", this->opcode,
+                                         segmentNames[this->segment],
+                                         MemDataType::label,
+                                         this->dest_vect[0].disassemble(),
+                                         this->dest_vect[1].disassemble(),
+                                         this->dest_vect[2].disassemble(),
+                                         this->addr.disassemble());
+            break;
           case 4:
             this->disassembly = csprintf("%s_%s_%s (%s,%s,%s,%s), %s",
                                          this->opcode,