Process post-adder first since C could be used for load-P

diff --git a/passes/pmgen/xilinx_dsp.cc b/passes/pmgen/xilinx_dsp.cc
index 9307b3d37a2911ef0317e53376ebde8d2450d1c1..1732a2d6ac74dadba04d67797873980ed9e730c6 100644 (file)
--- a/passes/pmgen/xilinx_dsp.cc
+++ b/passes/pmgen/xilinx_dsp.cc
@@ -49,8 +49,27 @@ void pack_xilinx_dsp(dict<SigBit, Cell*> &bit_to_driver, xilinx_dsp_pm &pm)
 
        Cell *cell = st.dsp;
        bit_to_driver.insert(std::make_pair(cell->getPort("\\P")[17], cell));
+       SigSpec C = st.sigC;
        SigSpec P = st.sigP;
 
+       if (st.addAB) {
+               log_assert(st.addAB->getParam("\\A_SIGNED").as_bool());
+               log_assert(st.addAB->getParam("\\B_SIGNED").as_bool());
+               log("  adder %s (%s)\n", log_id(st.addAB), log_id(st.addAB->type));
+
+               SigSpec &opmode = cell->connections_.at("\\OPMODE");
+               if (st.ffP && C == P) {
+                       C = SigSpec();
+                       opmode[4] = State::S0;
+               }
+               else
+                       opmode[4] = State::S1;
+               opmode[6] = State::S0;
+               opmode[5] = State::S1;
+
+               pm.autoremove(st.addAB);
+       }
+
        if (st.clock != SigBit())
        {
                cell->setPort("\\CLK", st.clock);
@@ -125,25 +144,10 @@ void pack_xilinx_dsp(dict<SigBit, Cell*> &bit_to_driver, xilinx_dsp_pm &pm)
                log("\n");
        }
 
-       if (st.addAB) {
-               log_assert(st.addAB->getParam("\\A_SIGNED").as_bool());
-               log_assert(st.addAB->getParam("\\B_SIGNED").as_bool());
-               log("  adder %s (%s)\n", log_id(st.addAB), log_id(st.addAB->type));
-
-               SigSpec C = st.sigC;
-               SigSpec &opmode = cell->connections_.at("\\OPMODE");
-               if (cell->getParam("\\PREG").as_bool() && C == P) {
-                       opmode[4] = State::S0;
-               }
-               else {
+       if (!C.empty()) {
+               if (GetSize(C) < 48)
                        C.extend_u0(48, true);
-                       cell->setPort("\\C", C);
-                       opmode[4] = State::S1;
-               }
-               opmode[6] = State::S0;
-               opmode[5] = State::S1;
-
-               pm.autoremove(st.addAB);
+               cell->setPort("\\C", C);
        }
 
        if (GetSize(P) < 48)