#include "swrast/swrast.h"
#include "drivers/common/meta.h"
+#include "intel_batchbuffer.h"
#include "intel_context.h"
#include "intel_blit.h"
#include "intel_clear.h"
#include "intel_fbo.h"
+#include "intel_mipmap_tree.h"
#include "intel_regions.h"
#define FILE_DEBUG_FLAG DEBUG_BLIT
}
}
+/**
+ * Implements fast depth clears on gen6+.
+ *
+ * Fast clears basically work by setting a flag in each of the subspans
+ * represented in the HiZ buffer that says "When you need the depth values for
+ * this subspan, it's the hardware's current clear value." Then later rendering
+ * can just use the static clear value instead of referencing memory.
+ *
+ * The tricky part of the implementation is that you have to have the clear
+ * value that was used on the depth buffer in place for all further rendering,
+ * at least until a resolve to the real depth buffer happens.
+ */
+static bool
+brw_fast_clear_depth(struct gl_context *ctx)
+{
+ struct intel_context *intel = intel_context(ctx);
+ struct gl_framebuffer *fb = ctx->DrawBuffer;
+ struct intel_renderbuffer *depth_irb =
+ intel_get_renderbuffer(fb, BUFFER_DEPTH);
+ struct intel_mipmap_tree *mt = depth_irb->mt;
+
+ if (intel->gen < 6)
+ return false;
+
+ if (!mt->hiz_mt)
+ return false;
+
+ /* We only handle full buffer clears -- otherwise you'd have to track whether
+ * a previous clear had happened at a different clear value and resolve it
+ * first.
+ */
+ if (ctx->Scissor.Enabled)
+ return false;
+
+ /* The rendered area has to be 8x4 samples, not resolved pixels, so we look
+ * at the miptree slice dimensions instead of renderbuffer size.
+ */
+ if (mt->level[depth_irb->mt_level].width % 8 != 0 ||
+ mt->level[depth_irb->mt_level].height % 4 != 0) {
+ return false;
+ }
+
+ uint32_t depth_clear_value;
+ switch (mt->format) {
+ case MESA_FORMAT_Z32_FLOAT_X24S8:
+ case MESA_FORMAT_S8_Z24:
+ /* From the Sandy Bridge PRM, volume 2 part 1, page 314:
+ *
+ * "[DevSNB+]: Several cases exist where Depth Buffer Clear cannot be
+ * enabled (the legacy method of clearing must be performed):
+ *
+ * - If the depth buffer format is D32_FLOAT_S8X24_UINT or
+ * D24_UNORM_S8_UINT.
+ */
+ return false;
+
+ case MESA_FORMAT_Z32_FLOAT:
+ depth_clear_value = float_as_int(ctx->Depth.Clear);
+ break;
+
+ case MESA_FORMAT_Z16:
+ /* From the Sandy Bridge PRM, volume 2 part 1, page 314:
+ *
+ * "[DevSNB+]: Several cases exist where Depth Buffer Clear cannot be
+ * enabled (the legacy method of clearing must be performed):
+ *
+ * - DevSNB{W/A}]: When depth buffer format is D16_UNORM and the
+ * width of the map (LOD0) is not multiple of 16, fast clear
+ * optimization must be disabled.
+ */
+ if (intel->gen == 6 && (mt->level[depth_irb->mt_level].width % 16) != 0)
+ return false;
+ /* FALLTHROUGH */
+
+ default:
+ depth_clear_value = fb->_DepthMax * ctx->Depth.Clear;
+ break;
+ }
+
+ /* If we're clearing to a new clear value, then we need to resolve any clear
+ * flags out of the HiZ buffer into the real depth buffer.
+ */
+ if (mt->depth_clear_value != depth_clear_value) {
+ intel_miptree_all_slices_resolve_depth(intel, mt);
+ mt->depth_clear_value = depth_clear_value;
+ }
+
+ /* From the Sandy Bridge PRM, volume 2 part 1, page 313:
+ *
+ * "If other rendering operations have preceded this clear, a
+ * PIPE_CONTROL with write cache flush enabled and Z-inhibit disabled
+ * must be issued before the rectangle primitive used for the depth
+ * buffer clear operation.
+ */
+ intel_batchbuffer_emit_mi_flush(intel);
+
+ intel_hiz_exec(intel, mt, depth_irb->mt_level, depth_irb->mt_layer,
+ GEN6_HIZ_OP_DEPTH_CLEAR);
+
+ if (intel->gen == 6) {
+ /* From the Sandy Bridge PRM, volume 2 part 1, page 314:
+ *
+ * "DevSNB, DevSNB-B{W/A}]: Depth buffer clear pass must be followed
+ * by a PIPE_CONTROL command with DEPTH_STALL bit set and Then
+ * followed by Depth FLUSH'
+ */
+ intel_batchbuffer_emit_mi_flush(intel);
+ }
+
+ /* Now, the entire HiZ buffer contains data that needs to be resolved to the
+ * entire depth buffer (so any previous resolve records should get tossed
+ * out).
+ */
+ intel_resolve_map_clear(&mt->hiz_map);
+ intel_renderbuffer_set_needs_depth_resolve(depth_irb);
+
+ return true;
+}
+
/**
* Called by ctx->Driver.Clear.
*/
intel->front_buffer_dirty = true;
}
+ intel_prepare_render(intel);
+
+ if (mask & BUFFER_BIT_DEPTH) {
+ if (brw_fast_clear_depth(ctx)) {
+ DBG("fast clear: depth\n");
+ mask &= ~BUFFER_BIT_DEPTH;
+ }
+ }
+
GLbitfield tri_mask = mask & (BUFFER_BITS_COLOR |
BUFFER_BIT_STENCIL |
BUFFER_BIT_DEPTH);
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