GHDL ?= ghdl
-GHDLFLAGS=--std=08 --work=unisim
+GHDLFLAGS=--std=08 --work=unisim -frelaxed
CFLAGS=-O3 -Wall
GHDLSYNTH ?= ghdl.so
core_tbs = multiply_tb divider_tb rotator_tb countzero_tb
soc_tbs = core_tb icache_tb dcache_tb dmi_dtm_tb wishbone_bram_tb
-soc_dram_tbs = core_dram_tb
+soc_dram_tbs = dram_tb core_dram_tb
$(soc_tbs): %: $(core_files) $(soc_files) $(soc_sim_files) $(soc_sim_obj_files) %.vhdl
$(GHDL) -c $(GHDLFLAGS) $(soc_sim_link) $(core_files) $(soc_files) $(soc_sim_files) $@.vhdl -e $@
--- /dev/null
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+library work;
+use work.common.all;
+use work.wishbone_types.all;
+
+entity dram_tb is
+ generic (
+ DRAM_INIT_FILE : string := "";
+ DRAM_INIT_SIZE : natural := 0
+ );
+end dram_tb;
+
+architecture behave of dram_tb is
+ signal clk, rst: std_logic;
+ signal clk_in, soc_rst : std_ulogic;
+
+ -- testbench signals
+ constant clk_period : time := 10 ns;
+
+ -- Sim DRAM
+ signal wb_in : wishbone_master_out;
+ signal wb_out : wishbone_slave_out;
+ signal wb_ctrl_in : wb_io_master_out;
+
+ subtype addr_t is std_ulogic_vector(wb_in.adr'left downto 0);
+ subtype data_t is std_ulogic_vector(wb_in.dat'left downto 0);
+ subtype sel_t is std_ulogic_vector(wb_in.sel'left downto 0);
+
+ -- Counter for acks
+ signal acks : integer := 0;
+ signal reset_acks : std_ulogic;
+
+ -- Read data fifo
+ signal rd_ready : std_ulogic := '0';
+ signal rd_valid : std_ulogic;
+ signal rd_data : data_t;
+begin
+
+ dram: entity work.litedram_wrapper
+ generic map(
+ DRAM_ABITS => 24,
+ DRAM_ALINES => 1,
+ PAYLOAD_FILE => DRAM_INIT_FILE,
+ PAYLOAD_SIZE => DRAM_INIT_SIZE
+ )
+ port map(
+ clk_in => clk_in,
+ rst => rst,
+ system_clk => clk,
+ system_reset => soc_rst,
+ core_alt_reset => open,
+ pll_locked => open,
+
+ wb_in => wb_in,
+ wb_out => wb_out,
+ wb_ctrl_in => wb_ctrl_in,
+ wb_ctrl_out => open,
+ wb_ctrl_is_csr => '0',
+ wb_ctrl_is_init => '0',
+
+ serial_tx => open,
+ serial_rx => '1',
+
+ init_done => open,
+ init_error => open,
+
+ ddram_a => open,
+ ddram_ba => open,
+ ddram_ras_n => open,
+ ddram_cas_n => open,
+ ddram_we_n => open,
+ ddram_cs_n => open,
+ ddram_dm => open,
+ ddram_dq => open,
+ ddram_dqs_p => open,
+ ddram_dqs_n => open,
+ ddram_clk_p => open,
+ ddram_clk_n => open,
+ ddram_cke => open,
+ ddram_odt => open,
+ ddram_reset_n => open
+ );
+
+ clk_process: process
+ begin
+ clk_in <= '0';
+ wait for clk_period/2;
+ clk_in <= '1';
+ wait for clk_period/2;
+ end process;
+
+ rst_process: process
+ begin
+ rst <= '1';
+ wait for 10*clk_period;
+ rst <= '0';
+ wait;
+ end process;
+
+ wb_ctrl_in.cyc <= '0';
+ wb_ctrl_in.stb <= '0';
+
+ -- Read data receive queue
+ data_queue: entity work.sync_fifo
+ generic map (
+ DEPTH => 16,
+ WIDTH => rd_data'length
+ )
+ port map (
+ clk => clk,
+ reset => soc_rst or reset_acks,
+ rd_ready => rd_ready,
+ rd_valid => rd_valid,
+ rd_data => rd_data,
+ wr_ready => open,
+ wr_valid => wb_out.ack,
+ wr_data => wb_out.dat
+ );
+
+ recv_acks: process(clk)
+ begin
+ if rising_edge(clk) then
+ if rst = '1' or reset_acks = '1' then
+ acks <= 0;
+ elsif wb_out.ack = '1' then
+ acks <= acks + 1;
+-- report "WB ACK ! DATA=" & to_hstring(wb_out.dat);
+ end if;
+ end if;
+ end process;
+
+ sim: process
+ procedure wb_write(addr: addr_t; data: data_t; sel: sel_t) is
+ begin
+ wb_in.adr <= addr;
+ wb_in.sel <= sel;
+ wb_in.dat <= data;
+ wb_in.we <= '1';
+ wb_in.stb <= '1';
+ wb_in.cyc <= '1';
+ loop
+ wait until rising_edge(clk);
+ if wb_out.stall = '0' then
+ wb_in.stb <= '0';
+ exit;
+ end if;
+ end loop;
+ end procedure;
+
+ procedure wb_read(addr: addr_t) is
+ begin
+ wb_in.adr <= addr;
+ wb_in.sel <= x"ff";
+ wb_in.we <= '0';
+ wb_in.stb <= '1';
+ wb_in.cyc <= '1';
+ loop
+ wait until rising_edge(clk);
+ if wb_out.stall = '0' then
+ wb_in.stb <= '0';
+ exit;
+ end if;
+ end loop;
+ end procedure;
+
+ procedure wait_acks(count: integer) is
+ begin
+ wait until acks = count;
+ wait until rising_edge(clk);
+ end procedure;
+
+ procedure clr_acks is
+ begin
+ reset_acks <= '1';
+ wait until rising_edge(clk);
+ reset_acks <= '0';
+ end procedure;
+
+ procedure read_data(data: out data_t) is
+ begin
+ assert rd_valid = '1' report "No data to read" severity failure;
+ rd_ready <= '1';
+ wait until rising_edge(clk);
+ rd_ready <= '0';
+ data := rd_data;
+ end procedure;
+
+ function add_off(a: addr_t; off: integer) return addr_t is
+ begin
+ return addr_t(unsigned(a) + off);
+ end function;
+
+ function make_pattern(num : integer) return data_t is
+ variable r : data_t;
+ variable t,b : integer;
+ begin
+ for i in 0 to (data_t'length/8)-1 loop
+ t := (i+1)*8-1;
+ b := i*8;
+ r(t downto b) := std_ulogic_vector(to_unsigned(num+1, 8));
+ end loop;
+ return r;
+ end function;
+
+ procedure check_data(p: data_t) is
+ variable d : data_t;
+ begin
+ read_data(d);
+ assert d = p report "bad data, want " & to_hstring(p) &
+ " got " & to_hstring(d) severity failure;
+ end procedure;
+
+ variable a : addr_t := (others => '0');
+ variable d : data_t := (others => '0');
+ variable d1 : data_t := (others => '0');
+ begin
+ reset_acks <= '0';
+ rst <= '1';
+ wait until rising_edge(clk_in);
+ wait until rising_edge(clk_in);
+ wait until rising_edge(clk_in);
+ wait until rising_edge(clk_in);
+ wait until rising_edge(clk_in);
+ rst <= '0';
+ wait until rising_edge(clk_in);
+ wait until soc_rst = '0';
+ wait until rising_edge(clk);
+
+ report "Simple write miss...";
+ clr_acks;
+ wb_write(a, x"0123456789abcdef", x"ff");
+ wait_acks(1);
+
+ report "Simple read miss...";
+ clr_acks;
+ wb_read(a);
+ wait_acks(1);
+ read_data(d);
+ assert d = x"0123456789abcdef" report "bad data" severity failure;
+
+ report "Simple read hit...";
+ clr_acks;
+ wb_read(a);
+ wait_acks(1);
+ read_data(d);
+ assert d = x"0123456789abcdef" report "bad data" severity failure;
+
+ report "Back to back 4 stores 4 reads on hit...";
+ clr_acks;
+ for i in 0 to 3 loop
+ wb_write(add_off(a, i*8), make_pattern(i), x"ff");
+ end loop;
+ for i in 0 to 3 loop
+ wb_read(add_off(a, i*8));
+ end loop;
+ wait_acks(8);
+ for i in 0 to 7 loop
+ if i < 4 then
+ read_data(d);
+ else
+ check_data(make_pattern(i-4));
+ end if;
+ end loop;
+
+ report "Back to back 4 stores 4 reads on miss...";
+ a(10) := '1';
+ clr_acks;
+ for i in 0 to 3 loop
+ wb_write(add_off(a, i*8), make_pattern(i), x"ff");
+ end loop;
+ for i in 0 to 3 loop
+ wb_read(add_off(a, i*8));
+ end loop;
+ wait_acks(8);
+ for i in 0 to 7 loop
+ if i < 4 then
+ read_data(d);
+ else
+ check_data(make_pattern(i-4));
+ end if;
+ end loop;
+
+ report "Back to back interleaved 4 stores 4 reads on hit...";
+ a(10) := '1';
+ clr_acks;
+ for i in 0 to 3 loop
+ wb_write(add_off(a, i*8), make_pattern(i), x"ff");
+ wb_read(add_off(a, i*8));
+ end loop;
+ wait_acks(8);
+ for i in 0 to 3 loop
+ read_data(d);
+ check_data(make_pattern(i));
+ end loop;
+
+ std.env.finish;
+ end process;
+end architecture;
--- /dev/null
+[*]
+[*] GTKWave Analyzer v3.3.86 (w)1999-2017 BSI
+[*] Sun May 31 12:53:52 2020
+[*]
+[dumpfile] "/home/ANT.AMAZON.COM/benh/hackplace/microwatt/foo.ghw"
+[dumpfile_mtime] "Sun May 31 12:50:15 2020"
+[dumpfile_size] 1134118
+[savefile] "/home/ANT.AMAZON.COM/benh/hackplace/microwatt/litedram/extras/wave_tb.gtkw"
+[timestart] 1312950000
+[size] 2509 1371
+[pos] -1 -1
+*-24.248457 1386890000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[treeopen] top.
+[treeopen] top.dram_tb.
+[sst_width] 301
+[signals_width] 433
+[sst_expanded] 1
+[sst_vpaned_height] 410
+@28
+top.dram_tb.reset_acks
+@420
+top.dram_tb.acks
+@28
+top.dram_tb.rst
+top.dram_tb.clk
+@22
+#{top.dram_tb.wb_in.dat[63:0]} top.dram_tb.wb_in.dat[63] top.dram_tb.wb_in.dat[62] top.dram_tb.wb_in.dat[61] top.dram_tb.wb_in.dat[60] top.dram_tb.wb_in.dat[59] top.dram_tb.wb_in.dat[58] top.dram_tb.wb_in.dat[57] top.dram_tb.wb_in.dat[56] top.dram_tb.wb_in.dat[55] top.dram_tb.wb_in.dat[54] top.dram_tb.wb_in.dat[53] top.dram_tb.wb_in.dat[52] top.dram_tb.wb_in.dat[51] top.dram_tb.wb_in.dat[50] top.dram_tb.wb_in.dat[49] top.dram_tb.wb_in.dat[48] top.dram_tb.wb_in.dat[47] top.dram_tb.wb_in.dat[46] top.dram_tb.wb_in.dat[45] top.dram_tb.wb_in.dat[44] top.dram_tb.wb_in.dat[43] top.dram_tb.wb_in.dat[42] top.dram_tb.wb_in.dat[41] top.dram_tb.wb_in.dat[40] top.dram_tb.wb_in.dat[39] top.dram_tb.wb_in.dat[38] top.dram_tb.wb_in.dat[37] top.dram_tb.wb_in.dat[36] top.dram_tb.wb_in.dat[35] top.dram_tb.wb_in.dat[34] top.dram_tb.wb_in.dat[33] top.dram_tb.wb_in.dat[32] top.dram_tb.wb_in.dat[31] top.dram_tb.wb_in.dat[30] top.dram_tb.wb_in.dat[29] top.dram_tb.wb_in.dat[28] top.dram_tb.wb_in.dat[27] top.dram_tb.wb_in.dat[26] top.dram_tb.wb_in.dat[25] top.dram_tb.wb_in.dat[24] top.dram_tb.wb_in.dat[23] top.dram_tb.wb_in.dat[22] top.dram_tb.wb_in.dat[21] top.dram_tb.wb_in.dat[20] top.dram_tb.wb_in.dat[19] top.dram_tb.wb_in.dat[18] top.dram_tb.wb_in.dat[17] top.dram_tb.wb_in.dat[16] top.dram_tb.wb_in.dat[15] top.dram_tb.wb_in.dat[14] top.dram_tb.wb_in.dat[13] top.dram_tb.wb_in.dat[12] top.dram_tb.wb_in.dat[11] top.dram_tb.wb_in.dat[10] top.dram_tb.wb_in.dat[9] top.dram_tb.wb_in.dat[8] top.dram_tb.wb_in.dat[7] top.dram_tb.wb_in.dat[6] top.dram_tb.wb_in.dat[5] top.dram_tb.wb_in.dat[4] top.dram_tb.wb_in.dat[3] top.dram_tb.wb_in.dat[2] top.dram_tb.wb_in.dat[1] top.dram_tb.wb_in.dat[0]
+#{top.dram_tb.wb_in.adr[31:0]} top.dram_tb.wb_in.adr[31] top.dram_tb.wb_in.adr[30] top.dram_tb.wb_in.adr[29] top.dram_tb.wb_in.adr[28] top.dram_tb.wb_in.adr[27] top.dram_tb.wb_in.adr[26] top.dram_tb.wb_in.adr[25] top.dram_tb.wb_in.adr[24] top.dram_tb.wb_in.adr[23] top.dram_tb.wb_in.adr[22] top.dram_tb.wb_in.adr[21] top.dram_tb.wb_in.adr[20] top.dram_tb.wb_in.adr[19] top.dram_tb.wb_in.adr[18] top.dram_tb.wb_in.adr[17] top.dram_tb.wb_in.adr[16] top.dram_tb.wb_in.adr[15] top.dram_tb.wb_in.adr[14] top.dram_tb.wb_in.adr[13] top.dram_tb.wb_in.adr[12] top.dram_tb.wb_in.adr[11] top.dram_tb.wb_in.adr[10] top.dram_tb.wb_in.adr[9] top.dram_tb.wb_in.adr[8] top.dram_tb.wb_in.adr[7] top.dram_tb.wb_in.adr[6] top.dram_tb.wb_in.adr[5] top.dram_tb.wb_in.adr[4] top.dram_tb.wb_in.adr[3] top.dram_tb.wb_in.adr[2] top.dram_tb.wb_in.adr[1] top.dram_tb.wb_in.adr[0]
+@23
+#{top.dram_tb.wb_in.sel[7:0]} top.dram_tb.wb_in.sel[7] top.dram_tb.wb_in.sel[6] top.dram_tb.wb_in.sel[5] top.dram_tb.wb_in.sel[4] top.dram_tb.wb_in.sel[3] top.dram_tb.wb_in.sel[2] top.dram_tb.wb_in.sel[1] top.dram_tb.wb_in.sel[0]
+@28
+top.dram_tb.wb_in.cyc
+top.dram_tb.wb_in.stb
+top.dram_tb.wb_in.we
+top.dram_tb.wb_out.ack
+top.dram_tb.wb_out.stall
+@22
+#{top.dram_tb.wb_out.dat[63:0]} top.dram_tb.wb_out.dat[63] top.dram_tb.wb_out.dat[62] top.dram_tb.wb_out.dat[61] top.dram_tb.wb_out.dat[60] top.dram_tb.wb_out.dat[59] top.dram_tb.wb_out.dat[58] top.dram_tb.wb_out.dat[57] top.dram_tb.wb_out.dat[56] top.dram_tb.wb_out.dat[55] top.dram_tb.wb_out.dat[54] top.dram_tb.wb_out.dat[53] top.dram_tb.wb_out.dat[52] top.dram_tb.wb_out.dat[51] top.dram_tb.wb_out.dat[50] top.dram_tb.wb_out.dat[49] top.dram_tb.wb_out.dat[48] top.dram_tb.wb_out.dat[47] top.dram_tb.wb_out.dat[46] top.dram_tb.wb_out.dat[45] top.dram_tb.wb_out.dat[44] top.dram_tb.wb_out.dat[43] top.dram_tb.wb_out.dat[42] top.dram_tb.wb_out.dat[41] top.dram_tb.wb_out.dat[40] top.dram_tb.wb_out.dat[39] top.dram_tb.wb_out.dat[38] top.dram_tb.wb_out.dat[37] top.dram_tb.wb_out.dat[36] top.dram_tb.wb_out.dat[35] top.dram_tb.wb_out.dat[34] top.dram_tb.wb_out.dat[33] top.dram_tb.wb_out.dat[32] top.dram_tb.wb_out.dat[31] top.dram_tb.wb_out.dat[30] top.dram_tb.wb_out.dat[29] top.dram_tb.wb_out.dat[28] top.dram_tb.wb_out.dat[27] top.dram_tb.wb_out.dat[26] top.dram_tb.wb_out.dat[25] top.dram_tb.wb_out.dat[24] top.dram_tb.wb_out.dat[23] top.dram_tb.wb_out.dat[22] top.dram_tb.wb_out.dat[21] top.dram_tb.wb_out.dat[20] top.dram_tb.wb_out.dat[19] top.dram_tb.wb_out.dat[18] top.dram_tb.wb_out.dat[17] top.dram_tb.wb_out.dat[16] top.dram_tb.wb_out.dat[15] top.dram_tb.wb_out.dat[14] top.dram_tb.wb_out.dat[13] top.dram_tb.wb_out.dat[12] top.dram_tb.wb_out.dat[11] top.dram_tb.wb_out.dat[10] top.dram_tb.wb_out.dat[9] top.dram_tb.wb_out.dat[8] top.dram_tb.wb_out.dat[7] top.dram_tb.wb_out.dat[6] top.dram_tb.wb_out.dat[5] top.dram_tb.wb_out.dat[4] top.dram_tb.wb_out.dat[3] top.dram_tb.wb_out.dat[2] top.dram_tb.wb_out.dat[1] top.dram_tb.wb_out.dat[0]
+@28
+top.dram_tb.rd_valid
+top.dram_tb.rd_ready
+@22
+#{top.dram_tb.rd_data[63:0]} top.dram_tb.rd_data[63] top.dram_tb.rd_data[62] top.dram_tb.rd_data[61] top.dram_tb.rd_data[60] top.dram_tb.rd_data[59] top.dram_tb.rd_data[58] top.dram_tb.rd_data[57] top.dram_tb.rd_data[56] top.dram_tb.rd_data[55] top.dram_tb.rd_data[54] top.dram_tb.rd_data[53] top.dram_tb.rd_data[52] top.dram_tb.rd_data[51] top.dram_tb.rd_data[50] top.dram_tb.rd_data[49] top.dram_tb.rd_data[48] top.dram_tb.rd_data[47] top.dram_tb.rd_data[46] top.dram_tb.rd_data[45] top.dram_tb.rd_data[44] top.dram_tb.rd_data[43] top.dram_tb.rd_data[42] top.dram_tb.rd_data[41] top.dram_tb.rd_data[40] top.dram_tb.rd_data[39] top.dram_tb.rd_data[38] top.dram_tb.rd_data[37] top.dram_tb.rd_data[36] top.dram_tb.rd_data[35] top.dram_tb.rd_data[34] top.dram_tb.rd_data[33] top.dram_tb.rd_data[32] top.dram_tb.rd_data[31] top.dram_tb.rd_data[30] top.dram_tb.rd_data[29] top.dram_tb.rd_data[28] top.dram_tb.rd_data[27] top.dram_tb.rd_data[26] top.dram_tb.rd_data[25] top.dram_tb.rd_data[24] top.dram_tb.rd_data[23] top.dram_tb.rd_data[22] top.dram_tb.rd_data[21] top.dram_tb.rd_data[20] top.dram_tb.rd_data[19] top.dram_tb.rd_data[18] top.dram_tb.rd_data[17] top.dram_tb.rd_data[16] top.dram_tb.rd_data[15] top.dram_tb.rd_data[14] top.dram_tb.rd_data[13] top.dram_tb.rd_data[12] top.dram_tb.rd_data[11] top.dram_tb.rd_data[10] top.dram_tb.rd_data[9] top.dram_tb.rd_data[8] top.dram_tb.rd_data[7] top.dram_tb.rd_data[6] top.dram_tb.rd_data[5] top.dram_tb.rd_data[4] top.dram_tb.rd_data[3] top.dram_tb.rd_data[2] top.dram_tb.rd_data[1] top.dram_tb.rd_data[0]
+@200
+-
+-
+-wrapper
+@28
+top.dram_tb.dram.accept_store
+@420
+top.dram_tb.dram.req_op
+top.dram_tb.dram.state
+@28
+top.dram_tb.dram.read_ack_1
+top.dram_tb.dram.read_ack_0
+top.dram_tb.dram.storeq_wr_valid
+top.dram_tb.dram.storeq_wr_ready
+top.dram_tb.dram.storeq_rd_valid
+top.dram_tb.dram.storeq_rd_ready
+top.dram_tb.dram.user_port0_rdata_ready
+top.dram_tb.dram.user_port0_rdata_valid
+top.dram_tb.dram.user_port0_wdata_ready
+top.dram_tb.dram.user_port0_wdata_valid
+top.dram_tb.dram.user_port0_cmd_we
+top.dram_tb.dram.user_port0_cmd_ready
+top.dram_tb.dram.user_port0_cmd_valid
+top.dram_tb.dram.refill_cmd_valid
+@420
+top.dram_tb.dram.req_index
+top.dram_tb.dram.req_hit_way
+@28
+top.dram_tb.dram.req_ad3
+@420
+top.dram_tb.dram.refill_row
+top.dram_tb.dram.refill_index
+top.dram_tb.dram.refill_way
+@28
+top.dram_tb.dram.system_clk
+[pattern_trace] 1
+[pattern_trace] 0
3c62ffff3c82ffff
38847ce838a57cd8
4bfffddd38637cf0
-6000000048000e99
+6000000048000e95
3c62ffff41920020
4bfffdc538637d20
8181000838210070
0100000000000000
3c4c000100000580
7c0802a6384295cc
-f821fec1480010ed
-3bc000013fe0c010
-7bff002063ff0028
-386000004bfffbd9
-7c0004ac4bfff6bd
-3f80c0107fc0ff2a
-7b9c0020639c0040
-7fc0e72a7c0004ac
-7c0004ac3ba00000
-386000017fa0ff2a
-392000024bfff68d
-7d20ff2a7c0004ac
-7fc0e72a7c0004ac
+480010e938600000
+3fe0c010f821fec1
+63ff00283bc00001
+4bfff6c17bff0020
+7fc0ff2a7c0004ac
+639c00403f80c010
+7c0004ac7b9c0020
+3ba000007fc0e72a
7fa0ff2a7c0004ac
-3b8100703c62ffff
-3e02ffff38637f48
-600000004bfff349
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//--------------------------------------------------------------------------------
-// Auto-generated by Migen (0d16e03) & LiteX (564d731a) on 2020-05-30 20:25:53
+// Auto-generated by Migen (0d16e03) & LiteX (564d731a) on 2020-05-31 17:48:50
//--------------------------------------------------------------------------------
module litedram_core(
input wire clk,
reg litedramcore_master_p3_rddata_en = 1'd0;
wire [31:0] litedramcore_master_p3_rddata;
wire litedramcore_master_p3_rddata_valid;
-reg [3:0] litedramcore_storage = 4'd0;
+reg [3:0] litedramcore_storage = 4'd1;
reg litedramcore_re = 1'd0;
reg [5:0] litedramcore_phaseinjector0_command_storage = 6'd0;
reg litedramcore_phaseinjector0_command_re = 1'd0;
a7ddrphy_bitslip15_value <= 4'd0;
a7ddrphy_rddata_en_last <= 8'd0;
a7ddrphy_wrdata_en_last <= 4'd0;
- litedramcore_storage <= 4'd0;
+ litedramcore_storage <= 4'd1;
litedramcore_re <= 1'd0;
litedramcore_phaseinjector0_command_storage <= 6'd0;
litedramcore_phaseinjector0_command_re <= 1'd0;
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//--------------------------------------------------------------------------------
-// Auto-generated by Migen (0d16e03) & LiteX (564d731a) on 2020-05-30 20:25:55
+// Auto-generated by Migen (0d16e03) & LiteX (564d731a) on 2020-05-31 17:48:52
//--------------------------------------------------------------------------------
module litedram_core(
input wire clk,
reg litedramcore_master_p3_rddata_en = 1'd0;
wire [31:0] litedramcore_master_p3_rddata;
wire litedramcore_master_p3_rddata_valid;
-reg [3:0] litedramcore_storage = 4'd0;
+reg [3:0] litedramcore_storage = 4'd1;
reg litedramcore_re = 1'd0;
reg [5:0] litedramcore_phaseinjector0_command_storage = 6'd0;
reg litedramcore_phaseinjector0_command_re = 1'd0;
a7ddrphy_bitslip15_value <= 4'd0;
a7ddrphy_rddata_en_last <= 8'd0;
a7ddrphy_wrdata_en_last <= 4'd0;
- litedramcore_storage <= 4'd0;
+ litedramcore_storage <= 4'd1;
litedramcore_re <= 1'd0;
litedramcore_phaseinjector0_command_storage <= 6'd0;
litedramcore_phaseinjector0_command_re <= 1'd0;
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//--------------------------------------------------------------------------------
-// Auto-generated by Migen (0d16e03) & LiteX (564d731a) on 2020-05-30 20:25:57
+// Auto-generated by Migen (0d16e03) & LiteX (564d731a) on 2020-05-31 17:48:54
//--------------------------------------------------------------------------------
module litedram_core(
input wire clk,
reg litedramcore_master_p3_rddata_en = 1'd0;
wire [31:0] litedramcore_master_p3_rddata;
wire litedramcore_master_p3_rddata_valid;
-reg [3:0] litedramcore_storage = 4'd0;
+reg [3:0] litedramcore_storage = 4'd1;
reg litedramcore_re = 1'd0;
reg [5:0] litedramcore_phaseinjector0_command_storage = 6'd0;
reg litedramcore_phaseinjector0_command_re = 1'd0;
ddrphy_new_banks_read_data7 <= 128'd0;
ddrphy_new_banks_read8 <= 1'd0;
ddrphy_new_banks_read_data8 <= 128'd0;
- litedramcore_storage <= 4'd0;
+ litedramcore_storage <= 4'd1;
litedramcore_re <= 1'd0;
litedramcore_phaseinjector0_command_storage <= 6'd0;
litedramcore_phaseinjector0_command_re <= 1'd0;
projects / microwatt.git / commitdiff