(no commit message)

diff --git a/openpower/sv/SimpleV_rationale.mdwn b/openpower/sv/SimpleV_rationale.mdwn
index 9d3f89a1a631c66c38e8af43104cc254d87ede08..d2586208e2c6202fbc2c0b6c84dfe84ebc702e21 100644 (file)
--- a/openpower/sv/SimpleV_rationale.mdwn
+++ b/openpower/sv/SimpleV_rationale.mdwn
@@ -261,7 +261,8 @@ The question then becomes: with all the duplication of arithmetic
 operations just to make the registers scalar or vector, why not
 leverage the *existing* Scalar ISA with some sort of "context"
 or prefix that augments its behaviour? Make "Scalar instruction"
-synonymous with "Scalar instruction" and through contextual
+synonymous with "Vector Element instruction" and through nothing
+more than contextual
 augmentation the Scalar ISA *becomes* the Vector ISA.
 Then, by not having to have any Vector instructions at all,
 the Instruction Decode