Fix debug

diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index 2409f3d919def4d26be7c980e4d4143ea136adac..193103747b7d16e267f971be5a6d17b433486453 100644 (file)
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -347,10 +347,10 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *module, std::string scrip
                log_assert(!design->module(ID($__abc9__)));
                {
                        AigerReader reader(design, ifs, ID($__abc9__), "" /* clk_name */, buffer.c_str() /* map_filename */, true /* wideports */);
-                       reader.parse_xaiger();
+                       reader.parse_xaiger(box_lookup);
                }
                ifs.close();
-               Pass::call(design, stringf("write_verilog -noexpr -norename"));
+               Pass::call_on_module(design, design->module(ID($__abc9__)), stringf("write_verilog -noexpr -norename -selected"));
                design->remove(design->module(ID($__abc9__)));
 #endif
 
@@ -421,7 +421,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *module, std::string scrip
                ifs.close();
 
 #if 0
-               Pass::call(design, stringf("write_verilog -noexpr -norename"));
+               Pass::call_on_module(design, design->module(ID($__abc9__)), stringf("write_verilog -noexpr -norename -selected"));
 #endif
 
                log_header(design, "Re-integrating ABC9 results.\n");