Faults: Pass the StaticInst involved, if any, to a Fault's invoke method.

Also move the "Fault" reference counted pointer type into a separate file,
sim/fault.hh. It would be better to name this less similarly to sim/faults.hh
to reduce confusion, but fault.hh matches the name of the type. We could change
Fault to FaultPtr to match other pointer types, and then changing the name of
the file would make more sense.

diff --git a/src/arch/alpha/faults.cc b/src/arch/alpha/faults.cc
index 3264fc8b274eefb6506964be3becc95c91a5def5..9d4eeda8afde7f4ce6992bb86d7ed35eb38b330c 100644 (file)
--- a/src/arch/alpha/faults.cc
+++ b/src/arch/alpha/faults.cc
@@ -110,7 +110,7 @@ FaultStat IntegerOverflowFault::_count;
 #if FULL_SYSTEM
 
 void
-AlphaFault::invoke(ThreadContext *tc)
+AlphaFault::invoke(ThreadContext *tc, StaticInstPtr inst)
 {
     FaultBase::invoke(tc);
     countStat()++;
@@ -130,14 +130,14 @@ AlphaFault::invoke(ThreadContext *tc)
 }
 
 void
-ArithmeticFault::invoke(ThreadContext *tc)
+ArithmeticFault::invoke(ThreadContext *tc, StaticInstPtr inst)
 {
     FaultBase::invoke(tc);
     panic("Arithmetic traps are unimplemented!");
 }
 
 void
-DtbFault::invoke(ThreadContext *tc)
+DtbFault::invoke(ThreadContext *tc, StaticInstPtr inst)
 {
     // Set fault address and flags.  Even though we're modeling an
     // EV5, we use the EV6 technique of not latching fault registers
@@ -150,9 +150,10 @@ DtbFault::invoke(ThreadContext *tc)
         tc->setMiscRegNoEffect(IPR_VA, vaddr);
 
         // set MM_STAT register flags
+        MachInst machInst = inst->machInst;
         tc->setMiscRegNoEffect(IPR_MM_STAT,
-            (((Opcode(tc->getInst()) & 0x3f) << 11) |
-             ((Ra(tc->getInst()) & 0x1f) << 6) |
+            (((Opcode(machInst) & 0x3f) << 11) |
+             ((Ra(machInst) & 0x1f) << 6) |
              (flags & 0x3f)));
 
         // set VA_FORM register with faulting formatted address
@@ -164,7 +165,7 @@ DtbFault::invoke(ThreadContext *tc)
 }
 
 void
-ItbFault::invoke(ThreadContext *tc)
+ItbFault::invoke(ThreadContext *tc, StaticInstPtr inst)
 {
     if (!tc->misspeculating()) {
         tc->setMiscRegNoEffect(IPR_ITB_TAG, pc);
@@ -178,7 +179,7 @@ ItbFault::invoke(ThreadContext *tc)
 #else
 
 void
-ItbPageFault::invoke(ThreadContext *tc)
+ItbPageFault::invoke(ThreadContext *tc, StaticInstPtr inst)
 {
     Process *p = tc->getProcessPtr();
     TlbEntry entry;
@@ -192,7 +193,7 @@ ItbPageFault::invoke(ThreadContext *tc)
 }
 
 void
-NDtbMissFault::invoke(ThreadContext *tc)
+NDtbMissFault::invoke(ThreadContext *tc, StaticInstPtr inst)
 {
     Process *p = tc->getProcessPtr();
     TlbEntry entry;

diff --git a/src/arch/alpha/faults.hh b/src/arch/alpha/faults.hh
index 9d90c7719b9ce58a744a9854c2331d81c15a1b0a..2b45a430c52bea61400eb827c802aa3bcd5b3aca 100644 (file)
--- a/src/arch/alpha/faults.hh
+++ b/src/arch/alpha/faults.hh
@@ -34,6 +34,7 @@
 
 #include "arch/alpha/pagetable.hh"
 #include "config/full_system.hh"
+#include "mem/request.hh"
 #include "sim/faults.hh"
 
 // The design of the "name" and "vect" functions is in sim/faults.hh
@@ -49,7 +50,8 @@ class AlphaFault : public FaultBase
     virtual bool setRestartAddress() {return true;}
   public:
 #if FULL_SYSTEM
-    void invoke(ThreadContext * tc);
+    void invoke(ThreadContext * tc,
+            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
 #endif
     virtual FaultVect vect() = 0;
     virtual FaultStat & countStat() = 0;
@@ -116,7 +118,8 @@ class ArithmeticFault : public AlphaFault
     FaultVect vect() {return _vect;}
     FaultStat & countStat() {return _count;}
 #if FULL_SYSTEM
-    void invoke(ThreadContext * tc);
+    void invoke(ThreadContext * tc,
+            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
 #endif
 };
 
@@ -151,7 +154,8 @@ class DtbFault : public AlphaFault
     FaultVect vect() = 0;
     FaultStat & countStat() = 0;
 #if FULL_SYSTEM
-    void invoke(ThreadContext * tc);
+    void invoke(ThreadContext * tc,
+            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
 #endif
 };
 
@@ -170,7 +174,8 @@ class NDtbMissFault : public DtbFault
     FaultVect vect() {return _vect;}
     FaultStat & countStat() {return _count;}
 #if !FULL_SYSTEM
-    void invoke(ThreadContext * tc);
+    void invoke(ThreadContext * tc,
+            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
 #endif
 };
 
@@ -249,7 +254,8 @@ class ItbFault : public AlphaFault
     FaultVect vect() = 0;
     FaultStat & countStat() = 0;
 #if FULL_SYSTEM
-    void invoke(ThreadContext * tc);
+    void invoke(ThreadContext * tc,
+            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
 #endif
 };
 
@@ -266,7 +272,8 @@ class ItbPageFault : public ItbFault
     FaultVect vect() {return _vect;}
     FaultStat & countStat() {return _count;}
 #if !FULL_SYSTEM
-    void invoke(ThreadContext * tc);
+    void invoke(ThreadContext * tc,
+            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
 #endif
 };
 

diff --git a/src/arch/alpha/isa.cc b/src/arch/alpha/isa.cc
index 8b6da3649457a75ebc711be4980d10a282833302..d89026ba79eba54d146235fa69a4cb8e326b5a66 100644 (file)
--- a/src/arch/alpha/isa.cc
+++ b/src/arch/alpha/isa.cc
@@ -28,6 +28,8 @@
  * Authors: Gabe Black
  */
 
+#include <cassert>
+
 #include "arch/alpha/isa.hh"
 #include "base/misc.hh"
 #include "cpu/thread_context.hh"

diff --git a/src/arch/alpha/process.cc b/src/arch/alpha/process.cc
index 431ef86c0639b3c1be17fb99724cc43df365789f..c65cf2d3771c198428701ca174f325090b2c9fab 100644 (file)
--- a/src/arch/alpha/process.cc
+++ b/src/arch/alpha/process.cc
@@ -36,6 +36,7 @@
 #include "base/misc.hh"
 #include "cpu/thread_context.hh"
 #include "mem/page_table.hh"
+#include "sim/byteswap.hh"
 #include "sim/process_impl.hh"
 #include "sim/system.hh"
 

diff --git a/src/arch/alpha/tlb.hh b/src/arch/alpha/tlb.hh
index b84c2645144102123e4955f96956dab9dfbde715..ed7e7ab6142fd58d07ce644a7100b55d79f9946b 100644 (file)
--- a/src/arch/alpha/tlb.hh
+++ b/src/arch/alpha/tlb.hh
@@ -42,7 +42,7 @@
 #include "base/statistics.hh"
 #include "mem/request.hh"
 #include "params/AlphaTLB.hh"
-#include "sim/faults.hh"
+#include "sim/fault.hh"
 #include "sim/tlb.hh"
 
 class ThreadContext;

diff --git a/src/arch/alpha/tru64/process.cc b/src/arch/alpha/tru64/process.cc
index 824e0413c86491a917a5457e4f09e13e0ee4c60e..9aae7e15563dc9e6b17c3f79a8870460bf3c724a 100644 (file)
--- a/src/arch/alpha/tru64/process.cc
+++ b/src/arch/alpha/tru64/process.cc
@@ -34,6 +34,7 @@
 #include "arch/alpha/tru64/process.hh"
 #include "cpu/thread_context.hh"
 #include "kern/tru64/tru64.hh"
+#include "sim/byteswap.hh"
 #include "sim/process.hh"
 #include "sim/syscall_emul.hh"
 

diff --git a/src/arch/arm/faults.cc b/src/arch/arm/faults.cc
index 2a6b7c359498db693eb3b0e408c4b4320ca6fc06..a5ecdad256ed1c4abd16aaecf0e8fcad9857e0fe 100644 (file)
--- a/src/arch/arm/faults.cc
+++ b/src/arch/arm/faults.cc
@@ -94,7 +94,7 @@ ArmFault::getVector(ThreadContext *tc)
 #if FULL_SYSTEM
 
 void 
-ArmFault::invoke(ThreadContext *tc)
+ArmFault::invoke(ThreadContext *tc, StaticInstPtr inst)
 {
     // ARM ARM B1.6.3
     FaultBase::invoke(tc);
@@ -150,7 +150,7 @@ ArmFault::invoke(ThreadContext *tc)
 }
 
 void
-Reset::invoke(ThreadContext *tc)
+Reset::invoke(ThreadContext *tc, StaticInstPtr inst)
 {
     tc->getCpuPtr()->clearInterrupts();
     tc->clearArchRegs();
@@ -160,7 +160,7 @@ Reset::invoke(ThreadContext *tc)
 #else
 
 void
-UndefinedInstruction::invoke(ThreadContext *tc)
+UndefinedInstruction::invoke(ThreadContext *tc, StaticInstPtr inst)
 {
     // If the mnemonic isn't defined this has to be an unknown instruction.
     assert(unknown || mnemonic != NULL);
@@ -177,7 +177,7 @@ UndefinedInstruction::invoke(ThreadContext *tc)
 }
 
 void
-SupervisorCall::invoke(ThreadContext *tc)
+SupervisorCall::invoke(ThreadContext *tc, StaticInstPtr inst)
 {
     // As of now, there isn't a 32 bit thumb version of this instruction.
     assert(!machInst.bigThumb);
@@ -203,7 +203,7 @@ SupervisorCall::invoke(ThreadContext *tc)
 
 template<class T>
 void
-AbortFault<T>::invoke(ThreadContext *tc)
+AbortFault<T>::invoke(ThreadContext *tc, StaticInstPtr inst)
 {
     ArmFaultVals<T>::invoke(tc);
     FSR fsr = 0;
@@ -217,7 +217,7 @@ AbortFault<T>::invoke(ThreadContext *tc)
 }
 
 void
-FlushPipe::invoke(ThreadContext *tc) {
+FlushPipe::invoke(ThreadContext *tc, StaticInstPtr inst) {
     DPRINTF(Faults, "Invoking FlushPipe Fault\n");
 
     // Set the PC to the next instruction of the faulting instruction.
@@ -229,8 +229,10 @@ FlushPipe::invoke(ThreadContext *tc) {
     tc->setNextMicroPC(1);
 }
 
-template void AbortFault<PrefetchAbort>::invoke(ThreadContext *tc);
-template void AbortFault<DataAbort>::invoke(ThreadContext *tc);
+template void AbortFault<PrefetchAbort>::invoke(ThreadContext *tc,
+                                                StaticInstPtr inst);
+template void AbortFault<DataAbort>::invoke(ThreadContext *tc,
+                                            StaticInstPtr inst);
 
 // return via SUBS pc, lr, xxx; rfe, movs, ldm
 

diff --git a/src/arch/arm/faults.hh b/src/arch/arm/faults.hh
index 3eef0e551766c8410b7bddd7e47f548a49bb8696..a68e7b2ef94c985235b05216fde6ac07183d6d83 100644 (file)
--- a/src/arch/arm/faults.hh
+++ b/src/arch/arm/faults.hh
@@ -108,7 +108,8 @@ class ArmFault : public FaultBase
     };
 
 #if FULL_SYSTEM
-    void invoke(ThreadContext *tc);
+    void invoke(ThreadContext *tc,
+            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
 #endif
     virtual FaultStat& countStat() = 0;
     virtual FaultOffset offset() = 0;
@@ -140,7 +141,8 @@ class Reset : public ArmFaultVals<Reset>
 #if FULL_SYSTEM
 {
   public:
-    void invoke(ThreadContext *tc);
+    void invoke(ThreadContext *tc,
+            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
 };
 #else
 {};
@@ -165,7 +167,8 @@ class UndefinedInstruction : public ArmFaultVals<UndefinedInstruction>
     {
     }
 
-    void invoke(ThreadContext *tc);
+    void invoke(ThreadContext *tc,
+            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
 #endif
 };
 
@@ -179,7 +182,8 @@ class SupervisorCall : public ArmFaultVals<SupervisorCall>
     SupervisorCall(ExtMachInst _machInst) : machInst(_machInst)
     {}
 
-    void invoke(ThreadContext *tc);
+    void invoke(ThreadContext *tc,
+            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
 #endif
 };
 
@@ -199,7 +203,8 @@ class AbortFault : public ArmFaultVals<T>
         domain(_domain), status(_status)
     {}
 
-    void invoke(ThreadContext *tc);
+    void invoke(ThreadContext *tc,
+            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
 };
 
 class PrefetchAbort : public AbortFault<PrefetchAbort>
@@ -232,7 +237,8 @@ class FlushPipe : public ArmFaultVals<FlushPipe>
 {
   public:
     FlushPipe() {}
-    void invoke(ThreadContext *tc);
+    void invoke(ThreadContext *tc,
+            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
 };
 
 static inline Fault genMachineCheckFault()

diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 5655c1265b212f20e835c4505d186fe14f46ef5a..22447184ed6f57aafdd09ce9417afe95c4e25f74 100644 (file)
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -39,6 +39,7 @@
  */
 
 #include "arch/arm/isa.hh"
+#include "sim/faults.hh"
 
 namespace ArmISA
 {

diff --git a/src/arch/arm/isa/includes.isa b/src/arch/arm/isa/includes.isa
index b3ad567dc0811347be8bf0e4edd123e73f37bb02..111552c78437a0d0787837f8dce09800fab7da36 100644 (file)
--- a/src/arch/arm/isa/includes.isa
+++ b/src/arch/arm/isa/includes.isa
@@ -59,6 +59,7 @@ output header {{
 #include "arch/arm/insts/vfp.hh"
 #include "arch/arm/isa_traits.hh"
 #include "mem/packet.hh"
+#include "sim/faults.hh"
 }};
 
 output decoder {{

diff --git a/src/arch/arm/nativetrace.cc b/src/arch/arm/nativetrace.cc
index e426d6611ff20b7bb7a3a2c0196c3f439a33ebcd..d97be88a25d36784d05b43bc21d261a1263d051c 100644 (file)
--- a/src/arch/arm/nativetrace.cc
+++ b/src/arch/arm/nativetrace.cc
@@ -45,6 +45,7 @@
 #include "arch/arm/nativetrace.hh"
 #include "cpu/thread_context.hh"
 #include "params/ArmNativeTrace.hh"
+#include "sim/byteswap.hh"
 
 namespace Trace {
 

diff --git a/src/arch/arm/process.cc b/src/arch/arm/process.cc
index e8dda1af07a5491252b13149c57232b6804a6114..636dd5310c8055c479b3883ec7bbf852092e40ef 100644 (file)
--- a/src/arch/arm/process.cc
+++ b/src/arch/arm/process.cc
@@ -50,6 +50,7 @@
 #include "cpu/thread_context.hh"
 #include "mem/page_table.hh"
 #include "mem/translating_port.hh"
+#include "sim/byteswap.hh"
 #include "sim/process_impl.hh"
 #include "sim/system.hh"
 

diff --git a/src/arch/arm/table_walker.hh b/src/arch/arm/table_walker.hh
index 680c93cba67d9083f8be246404bfbb8c1823ae6d..141bd7138391839a339bb630f5043dcfcfa77caf 100644 (file)
--- a/src/arch/arm/table_walker.hh
+++ b/src/arch/arm/table_walker.hh
@@ -48,8 +48,8 @@
 #include "mem/request.hh"
 #include "mem/request.hh"
 #include "params/ArmTableWalker.hh"
-#include "sim/faults.hh"
 #include "sim/eventq.hh"
+#include "sim/fault.hh"
 
 class DmaPort;
 class ThreadContext;

diff --git a/src/arch/arm/tlb.hh b/src/arch/arm/tlb.hh
index 6689845914ee937e271e501224fe16e2a8737534..eec52d9d294650e41499658799db92bb21a33e26 100644 (file)
--- a/src/arch/arm/tlb.hh
+++ b/src/arch/arm/tlb.hh
@@ -52,7 +52,7 @@
 #include "base/statistics.hh"
 #include "mem/request.hh"
 #include "params/ArmTLB.hh"
-#include "sim/faults.hh"
+#include "sim/fault.hh"
 #include "sim/tlb.hh"
 
 class ThreadContext;

diff --git a/src/arch/arm/utility.hh b/src/arch/arm/utility.hh
index 57b2423d39b50b119ba201830c45efd26680dace..2a30c5de26c4ff75adf32a13a799e2d6a260c1b8 100644 (file)
--- a/src/arch/arm/utility.hh
+++ b/src/arch/arm/utility.hh
@@ -48,6 +48,7 @@
 #include "arch/arm/miscregs.hh"
 #include "arch/arm/types.hh"
 #include "base/hashmap.hh"
+#include "base/misc.hh"
 #include "base/trace.hh"
 #include "base/types.hh"
 #include "cpu/thread_context.hh"

diff --git a/src/arch/mips/faults.cc b/src/arch/mips/faults.cc
index 68ee8645562dd865a337b737f0d126b923c4f8d1..9bb945dba18859da9fd1bb1eff9a26fc47947dca 100644 (file)
--- a/src/arch/mips/faults.cc
+++ b/src/arch/mips/faults.cc
@@ -217,7 +217,7 @@ MipsFault::setExceptionState(ThreadContext *tc, uint8_t excCode)
 }
 
 void
-ArithmeticFault::invoke(ThreadContext *tc)
+ArithmeticFault::invoke(ThreadContext *tc, StaticInstPtr inst)
 {
     DPRINTF(MipsPRA, "%s encountered.\n", name());
     setExceptionState(tc, 0xC);
@@ -237,7 +237,7 @@ ArithmeticFault::invoke(ThreadContext *tc)
 }
 
 void
-StoreAddressErrorFault::invoke(ThreadContext *tc)
+StoreAddressErrorFault::invoke(ThreadContext *tc, StaticInstPtr inst)
 {
     DPRINTF(MipsPRA, "%s encountered.\n", name());
     setExceptionState(tc, 0x5);
@@ -251,7 +251,7 @@ StoreAddressErrorFault::invoke(ThreadContext *tc)
 }
 
 void
-TrapFault::invoke(ThreadContext *tc)
+TrapFault::invoke(ThreadContext *tc, StaticInstPtr inst)
 {
     DPRINTF(MipsPRA, "%s encountered.\n", name());
     setExceptionState(tc, 0xD);
@@ -264,7 +264,7 @@ TrapFault::invoke(ThreadContext *tc)
 }
 
 void
-BreakpointFault::invoke(ThreadContext *tc)
+BreakpointFault::invoke(ThreadContext *tc, StaticInstPtr inst)
 {
     setExceptionState(tc, 0x9);
 
@@ -276,7 +276,7 @@ BreakpointFault::invoke(ThreadContext *tc)
 }
 
 void
-DtbInvalidFault::invoke(ThreadContext *tc)
+DtbInvalidFault::invoke(ThreadContext *tc, StaticInstPtr inst)
 {
     DPRINTF(MipsPRA, "%s encountered.\n", name());
 
@@ -301,7 +301,7 @@ DtbInvalidFault::invoke(ThreadContext *tc)
 }
 
 void
-AddressErrorFault::invoke(ThreadContext *tc)
+AddressErrorFault::invoke(ThreadContext *tc, StaticInstPtr inst)
 {
     DPRINTF(MipsPRA, "%s encountered.\n", name());
     setExceptionState(tc, 0x4);
@@ -315,7 +315,7 @@ AddressErrorFault::invoke(ThreadContext *tc)
 }
 
 void
-ItbInvalidFault::invoke(ThreadContext *tc)
+ItbInvalidFault::invoke(ThreadContext *tc, StaticInstPtr inst)
 {
     DPRINTF(MipsPRA, "%s encountered.\n", name());
     setExceptionState(tc, 0x2);
@@ -341,7 +341,7 @@ ItbInvalidFault::invoke(ThreadContext *tc)
 }
 
 void
-ItbRefillFault::invoke(ThreadContext *tc)
+ItbRefillFault::invoke(ThreadContext *tc, StaticInstPtr inst)
 {
     DPRINTF(MipsPRA, "%s encountered (%x).\n", name(), MISCREG_BADVADDR);
     Addr HandlerBase;
@@ -371,7 +371,7 @@ ItbRefillFault::invoke(ThreadContext *tc)
 }
 
 void
-DtbRefillFault::invoke(ThreadContext *tc)
+DtbRefillFault::invoke(ThreadContext *tc, StaticInstPtr inst)
 {
     // Set new PC
     DPRINTF(MipsPRA, "%s encountered.\n", name());
@@ -404,7 +404,7 @@ DtbRefillFault::invoke(ThreadContext *tc)
 }
 
 void
-TLBModifiedFault::invoke(ThreadContext *tc)
+TLBModifiedFault::invoke(ThreadContext *tc, StaticInstPtr inst)
 {
     DPRINTF(MipsPRA, "%s encountered.\n", name());
     tc->setMiscRegNoEffect(MISCREG_BADVADDR, badVAddr);
@@ -428,7 +428,7 @@ TLBModifiedFault::invoke(ThreadContext *tc)
 }
 
 void
-SystemCallFault::invoke(ThreadContext *tc)
+SystemCallFault::invoke(ThreadContext *tc, StaticInstPtr inst)
 {
     DPRINTF(MipsPRA, "%s encountered.\n", name());
     setExceptionState(tc, 0x8);
@@ -441,7 +441,7 @@ SystemCallFault::invoke(ThreadContext *tc)
 }
 
 void
-InterruptFault::invoke(ThreadContext *tc)
+InterruptFault::invoke(ThreadContext *tc, StaticInstPtr inst)
 {
 #if  FULL_SYSTEM
     DPRINTF(MipsPRA, "%s encountered.\n", name());
@@ -464,7 +464,7 @@ InterruptFault::invoke(ThreadContext *tc)
 #endif // FULL_SYSTEM
 
 void
-ResetFault::invoke(ThreadContext *tc)
+ResetFault::invoke(ThreadContext *tc, StaticInstPtr inst)
 {
 #if FULL_SYSTEM
     DPRINTF(MipsPRA, "%s encountered.\n", name());
@@ -482,7 +482,7 @@ ResetFault::invoke(ThreadContext *tc)
 }
 
 void
-ReservedInstructionFault::invoke(ThreadContext *tc)
+ReservedInstructionFault::invoke(ThreadContext *tc, StaticInstPtr inst)
 {
 #if  FULL_SYSTEM
     DPRINTF(MipsPRA, "%s encountered.\n", name());
@@ -497,21 +497,21 @@ ReservedInstructionFault::invoke(ThreadContext *tc)
 }
 
 void
-ThreadFault::invoke(ThreadContext *tc)
+ThreadFault::invoke(ThreadContext *tc, StaticInstPtr inst)
 {
     DPRINTF(MipsPRA, "%s encountered.\n", name());
     panic("%s encountered.\n", name());
 }
 
 void
-DspStateDisabledFault::invoke(ThreadContext *tc)
+DspStateDisabledFault::invoke(ThreadContext *tc, StaticInstPtr inst)
 {
     DPRINTF(MipsPRA, "%s encountered.\n", name());
     panic("%s encountered.\n", name());
 }
 
 void
-CoprocessorUnusableFault::invoke(ThreadContext *tc)
+CoprocessorUnusableFault::invoke(ThreadContext *tc, StaticInstPtr inst)
 {
 #if FULL_SYSTEM
     DPRINTF(MipsPRA, "%s encountered.\n", name());

diff --git a/src/arch/mips/faults.hh b/src/arch/mips/faults.hh
index 7a001d390bac93812804aeee165b4abd50818196..083aa5939804cfabd0d73836b2b1f2a8457c16a3 100644 (file)
--- a/src/arch/mips/faults.hh
+++ b/src/arch/mips/faults.hh
@@ -53,7 +53,9 @@ class MipsFault : public FaultBase
     Addr entryHiVPN2X;
     Addr contextBadVPN2;
 #if FULL_SYSTEM
-    void invoke(ThreadContext * tc) {};
+    void invoke(ThreadContext * tc,
+            StaticInst::StaticInstPtr inst = StaticInst::nullStaticInstPtr)
+    {}
     void setExceptionState(ThreadContext *, uint8_t);
     void setHandlerPC(Addr, ThreadContext *);
 #endif
@@ -111,7 +113,8 @@ class AddressErrorFault : public MipsFault
     FaultVect vect() {return _vect;}
     FaultStat & countStat() {return _count;}
 #if FULL_SYSTEM
-    void invoke(ThreadContext * tc);
+    void invoke(ThreadContext * tc,
+            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
 #endif
 
 };
@@ -127,7 +130,8 @@ class StoreAddressErrorFault : public MipsFault
     FaultVect vect() {return _vect;}
     FaultStat & countStat() {return _count;}
 #if FULL_SYSTEM
-    void invoke(ThreadContext * tc);
+    void invoke(ThreadContext * tc,
+            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
 #endif
 };
 
@@ -155,7 +159,8 @@ class TLBRefillIFetchFault : public MipsFault
     FaultName name() const {return _name;}
     FaultVect vect() {return _vect;}
     FaultStat & countStat() {return _count;}
-    void invoke(ThreadContext * tc);
+    void invoke(ThreadContext * tc,
+            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
 };
 
 class TLBInvalidIFetchFault : public MipsFault
@@ -169,7 +174,8 @@ class TLBInvalidIFetchFault : public MipsFault
     FaultName name() const {return _name;}
     FaultVect vect() {return _vect;}
     FaultStat & countStat() {return _count;}
-    void invoke(ThreadContext * tc);
+    void invoke(ThreadContext * tc,
+            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
 };
 
 class NDtbMissFault : public MipsFault
@@ -231,7 +237,8 @@ class CacheErrorFault : public MipsFault
     FaultName name() const {return _name;}
     FaultVect vect() {return _vect;}
     FaultStat & countStat() {return _count;}
-    void invoke(ThreadContext * tc);
+    void invoke(ThreadContext * tc,
+            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
 };
 
 
@@ -257,7 +264,8 @@ class ResetFault : public MipsFault
     FaultName name() const {return _name;}
     FaultVect vect() {return _vect;}
     FaultStat & countStat() {return _count;}
-    void invoke(ThreadContext * tc);
+    void invoke(ThreadContext * tc,
+            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
 
 };
 
@@ -271,7 +279,8 @@ class SystemCallFault : public MipsFault
     FaultName name() const {return _name;}
     FaultVect vect() {return _vect;}
     FaultStat & countStat() {return _count;}
-    void invoke(ThreadContext * tc);
+    void invoke(ThreadContext * tc,
+            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
 };
 
 class SoftResetFault : public MipsFault
@@ -284,7 +293,8 @@ class SoftResetFault : public MipsFault
     FaultName name() const {return _name;}
     FaultVect vect() {return _vect;}
     FaultStat & countStat() {return _count;}
-    void invoke(ThreadContext * tc);
+    void invoke(ThreadContext * tc,
+            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
 };
 
 class DebugSingleStep : public MipsFault
@@ -297,7 +307,8 @@ class DebugSingleStep : public MipsFault
     FaultName name() const {return _name;}
     FaultVect vect() {return _vect;}
     FaultStat & countStat() {return _count;}
-    void invoke(ThreadContext * tc);
+    void invoke(ThreadContext * tc,
+            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
 };
 
 class DebugInterrupt : public MipsFault
@@ -310,7 +321,8 @@ class DebugInterrupt : public MipsFault
     FaultName name() const {return _name;}
     FaultVect vect() {return _vect;}
     FaultStat & countStat() {return _count;}
-    void invoke(ThreadContext * tc);
+    void invoke(ThreadContext * tc,
+            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
 };
 
 class CoprocessorUnusableFault : public MipsFault
@@ -324,7 +336,8 @@ class CoprocessorUnusableFault : public MipsFault
     FaultName name() const {return _name;}
     FaultVect vect() {return _vect;}
     FaultStat & countStat() {return _count;}
-    void invoke(ThreadContext * tc);
+    void invoke(ThreadContext * tc,
+            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
     CoprocessorUnusableFault(int _procid){ coProcID = _procid;}
 };
 
@@ -338,7 +351,8 @@ class ReservedInstructionFault : public MipsFault
     FaultName name() const {return _name;}
     FaultVect vect() {return _vect;}
     FaultStat & countStat() {return _count;}
-    void invoke(ThreadContext * tc);
+    void invoke(ThreadContext * tc,
+            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
 };
 
 class ThreadFault : public MipsFault
@@ -351,7 +365,8 @@ class ThreadFault : public MipsFault
     FaultName name() const {return _name;}
     FaultVect vect() {return _vect;}
     FaultStat & countStat() {return _count;}
-    void invoke(ThreadContext * tc);
+    void invoke(ThreadContext * tc,
+            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
 };
 
 class ArithmeticFault : public MipsFault
@@ -367,7 +382,8 @@ class ArithmeticFault : public MipsFault
     FaultVect vect() {return _vect;}
     FaultStat & countStat() {return _count;}
 #if FULL_SYSTEM
-    void invoke(ThreadContext * tc);
+    void invoke(ThreadContext * tc,
+            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
 #endif
 };
 
@@ -385,7 +401,8 @@ class InterruptFault : public MipsFault
     FaultStat & countStat() {return _count;}
 
 #if FULL_SYSTEM
-    void invoke(ThreadContext * tc);
+    void invoke(ThreadContext * tc,
+            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
 #endif
 };
 
@@ -400,7 +417,8 @@ class TrapFault : public MipsFault
     FaultVect vect() {return _vect;}
     FaultStat & countStat() {return _count;}
 #if FULL_SYSTEM
-    void invoke(ThreadContext * tc);
+    void invoke(ThreadContext * tc,
+            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
 #endif
 };
 
@@ -415,7 +433,8 @@ class BreakpointFault : public MipsFault
     FaultVect vect() {return _vect;}
     FaultStat & countStat() {return _count;}
 #if FULL_SYSTEM
-    void invoke(ThreadContext * tc);
+    void invoke(ThreadContext * tc,
+            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
 #endif
 };
 
@@ -430,7 +449,8 @@ class ItbRefillFault : public MipsFault
     FaultVect vect() {return _vect;}
     FaultStat & countStat() {return _count;}
 #if FULL_SYSTEM
-    void invoke(ThreadContext * tc);
+    void invoke(ThreadContext * tc,
+            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
 #endif
 };
 
@@ -445,7 +465,8 @@ class DtbRefillFault : public MipsFault
     FaultVect vect() {return _vect;}
     FaultStat & countStat() {return _count;}
 #if FULL_SYSTEM
-    void invoke(ThreadContext * tc);
+    void invoke(ThreadContext * tc,
+            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
 #endif
 };
 
@@ -460,7 +481,8 @@ class ItbPageFault : public MipsFault
     FaultVect vect() {return _vect;}
     FaultStat & countStat() {return _count;}
 #if FULL_SYSTEM
-    void invoke(ThreadContext * tc);
+    void invoke(ThreadContext * tc,
+            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
 #endif
 };
 
@@ -475,7 +497,8 @@ class ItbInvalidFault : public MipsFault
     FaultVect vect() {return _vect;}
     FaultStat & countStat() {return _count;}
 #if FULL_SYSTEM
-    void invoke(ThreadContext * tc);
+    void invoke(ThreadContext * tc,
+            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
 #endif
 };
 
@@ -490,7 +513,8 @@ class TLBModifiedFault : public MipsFault
     FaultVect vect() {return _vect;}
     FaultStat & countStat() {return _count;}
 #if FULL_SYSTEM
-    void invoke(ThreadContext * tc);
+    void invoke(ThreadContext * tc,
+            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
 #endif
 };
 
@@ -505,7 +529,8 @@ class DtbInvalidFault : public MipsFault
     FaultVect vect() {return _vect;}
     FaultStat & countStat() {return _count;}
 #if FULL_SYSTEM
-    void invoke(ThreadContext * tc);
+    void invoke(ThreadContext * tc,
+            StaticInst::StaticInstPtr inst = nullStaticInstPtr);
 #endif
 };
 
@@ -567,7 +592,8 @@ class DspStateDisabledFault : public MipsFault
     FaultName name() const {return _name;}
     FaultVect vect() {return _vect;}
     FaultStat & countStat() {return _count;}
-    void invoke(ThreadContext * tc);
+    void invoke(ThreadContext * tc,
+            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
 };
 
 } // MipsISA namespace

diff --git a/src/arch/mips/isa.hh b/src/arch/mips/isa.hh
index 3f7afcdd0d6cb76352484c75071bc052a939a9c6..6adf6bddc8176bc03f21f371ec07f20714ee05ad 100644 (file)
--- a/src/arch/mips/isa.hh
+++ b/src/arch/mips/isa.hh
@@ -38,7 +38,7 @@
 #include "arch/mips/registers.hh"
 #include "arch/mips/types.hh"
 #include "sim/eventq.hh"
-#include "sim/faults.hh"
+#include "sim/fault.hh"
 
 class BaseCPU;
 class Checkpoint;

diff --git a/src/arch/mips/tlb.hh b/src/arch/mips/tlb.hh
index e301cf666a56db9e9a4a1d57c7344dbeb6ccceb1..cb2e434cb6a562d753b70dcb9578a54299899547 100644 (file)
--- a/src/arch/mips/tlb.hh
+++ b/src/arch/mips/tlb.hh
@@ -44,7 +44,7 @@
 #include "base/statistics.hh"
 #include "mem/request.hh"
 #include "params/MipsTLB.hh"
-#include "sim/faults.hh"
+#include "sim/fault.hh"
 #include "sim/tlb.hh"
 #include "sim/sim_object.hh"
 

diff --git a/src/arch/mips/utility.cc b/src/arch/mips/utility.cc
index ac90ce45e8ff9d8d3bb4ae7c8ce774fbf29c6f92..ab6a00af379a9173677497db5d3b1af6858963ad 100644 (file)
--- a/src/arch/mips/utility.cc
+++ b/src/arch/mips/utility.cc
@@ -28,6 +28,8 @@
  * Authors: Korey Sewell
  */
 
+#include <cmath>
+
 #include "arch/mips/isa_traits.hh"
 #include "arch/mips/utility.hh"
 #include "config/full_system.hh"

diff --git a/src/arch/power/tlb.hh b/src/arch/power/tlb.hh
index 4445995fcd2c73aedbef61fa384acb9c4926cbe4..8431b9ad199a99a3746004062bad569b3101898f 100644 (file)
--- a/src/arch/power/tlb.hh
+++ b/src/arch/power/tlb.hh
@@ -46,7 +46,7 @@
 #include "base/statistics.hh"
 #include "mem/request.hh"
 #include "params/PowerTLB.hh"
-#include "sim/faults.hh"
+#include "sim/fault.hh"
 #include "sim/tlb.hh"
 
 class ThreadContext;

diff --git a/src/arch/sparc/faults.cc b/src/arch/sparc/faults.cc
index 9c189d164f61bdef98b7eff03543e87fc722218d..df0a283b951b89e6999bad91fd1279a4d5be0d88 100644 (file)
--- a/src/arch/sparc/faults.cc
+++ b/src/arch/sparc/faults.cc
@@ -505,7 +505,7 @@ void getPrivVector(ThreadContext * tc, Addr & PC, Addr & NPC, MiscReg TT, MiscRe
 
 #if FULL_SYSTEM
 
-void SparcFaultBase::invoke(ThreadContext * tc)
+void SparcFaultBase::invoke(ThreadContext * tc, StaticInstPtr inst)
 {
     //panic("Invoking a second fault!\n");
     FaultBase::invoke(tc);
@@ -559,7 +559,7 @@ void SparcFaultBase::invoke(ThreadContext * tc)
     tc->setNextNPC(NPC + sizeof(MachInst));
 }
 
-void PowerOnReset::invoke(ThreadContext * tc)
+void PowerOnReset::invoke(ThreadContext * tc, StaticInstPtr inst)
 {
     //For SPARC, when a system is first started, there is a power
     //on reset Trap which sets the processor into the following state.
@@ -620,7 +620,8 @@ void PowerOnReset::invoke(ThreadContext * tc)
 
 #else // !FULL_SYSTEM
 
-void FastInstructionAccessMMUMiss::invoke(ThreadContext *tc)
+void FastInstructionAccessMMUMiss::invoke(ThreadContext *tc,
+                                          StaticInstPtr inst)
 {
     Process *p = tc->getProcessPtr();
     TlbEntry entry;
@@ -634,7 +635,7 @@ void FastInstructionAccessMMUMiss::invoke(ThreadContext *tc)
     }
 }
 
-void FastDataAccessMMUMiss::invoke(ThreadContext *tc)
+void FastDataAccessMMUMiss::invoke(ThreadContext *tc, StaticInstPtr inst)
 {
     Process *p = tc->getProcessPtr();
     TlbEntry entry;
@@ -652,7 +653,7 @@ void FastDataAccessMMUMiss::invoke(ThreadContext *tc)
     }
 }
 
-void SpillNNormal::invoke(ThreadContext *tc)
+void SpillNNormal::invoke(ThreadContext *tc, StaticInstPtr inst)
 {
     doNormalFault(tc, trapType(), false);
 
@@ -669,7 +670,7 @@ void SpillNNormal::invoke(ThreadContext *tc)
     tc->setNextNPC(spillStart + 2*sizeof(MachInst));
 }
 
-void FillNNormal::invoke(ThreadContext *tc)
+void FillNNormal::invoke(ThreadContext *tc, StaticInstPtr inst)
 {
     doNormalFault(tc, trapType(), false);
 
@@ -686,7 +687,7 @@ void FillNNormal::invoke(ThreadContext *tc)
     tc->setNextNPC(fillStart + 2*sizeof(MachInst));
 }
 
-void TrapInstruction::invoke(ThreadContext *tc)
+void TrapInstruction::invoke(ThreadContext *tc, StaticInstPtr inst)
 {
     //In SE, this mechanism is how the process requests a service from the
     //operating system. We'll get the process object from the thread context

diff --git a/src/arch/sparc/faults.hh b/src/arch/sparc/faults.hh
index 20dd113c6214adb8d25fd353d7cfe03af4839e88..dca10d1750203ba80f24a97ff09a2504269e3963 100644 (file)
--- a/src/arch/sparc/faults.hh
+++ b/src/arch/sparc/faults.hh
@@ -33,6 +33,7 @@
 #define __SPARC_FAULTS_HH__
 
 #include "config/full_system.hh"
+#include "cpu/static_inst.hh"
 #include "sim/faults.hh"
 
 // The design of the "name" and "vect" functions is in sim/faults.hh
@@ -66,7 +67,8 @@ class SparcFaultBase : public FaultBase
         FaultStat count;
     };
 #if FULL_SYSTEM
-    void invoke(ThreadContext * tc);
+    void invoke(ThreadContext * tc,
+            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
 #endif
     virtual TrapType trapType() = 0;
     virtual FaultPriority priority() = 0;
@@ -92,7 +94,10 @@ class SparcFault : public SparcFaultBase
 
 class PowerOnReset : public SparcFault<PowerOnReset>
 {
-    void invoke(ThreadContext * tc);
+#if FULL_SYSTEM
+    void invoke(ThreadContext * tc,
+            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
+#endif
 };
 
 class WatchDogReset : public SparcFault<WatchDogReset> {};
@@ -210,7 +215,8 @@ class FastInstructionAccessMMUMiss :
   public:
     FastInstructionAccessMMUMiss(Addr addr) : vaddr(addr)
     {}
-    void invoke(ThreadContext * tc);
+    void invoke(ThreadContext * tc,
+            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
 #endif
 };
 
@@ -222,7 +228,8 @@ class FastDataAccessMMUMiss : public SparcFault<FastDataAccessMMUMiss>
   public:
     FastDataAccessMMUMiss(Addr addr) : vaddr(addr)
     {}
-    void invoke(ThreadContext * tc);
+    void invoke(ThreadContext * tc,
+            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
 #endif
 };
 
@@ -242,7 +249,8 @@ class SpillNNormal : public EnumeratedFault<SpillNNormal>
     SpillNNormal(uint32_t n) : EnumeratedFault<SpillNNormal>(n) {;}
     //These need to be handled specially to enable spill traps in SE
 #if !FULL_SYSTEM
-    void invoke(ThreadContext * tc);
+    void invoke(ThreadContext * tc,
+            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
 #endif
 };
 
@@ -258,7 +266,8 @@ class FillNNormal : public EnumeratedFault<FillNNormal>
     FillNNormal(uint32_t n) : EnumeratedFault<FillNNormal>(n) {;}
     //These need to be handled specially to enable fill traps in SE
 #if !FULL_SYSTEM
-    void invoke(ThreadContext * tc);
+    void invoke(ThreadContext * tc,
+            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
 #endif
 };
 
@@ -274,7 +283,8 @@ class TrapInstruction : public EnumeratedFault<TrapInstruction>
     TrapInstruction(uint32_t n) : EnumeratedFault<TrapInstruction>(n) {;}
     //In SE, trap instructions are requesting services from the OS.
 #if !FULL_SYSTEM
-    void invoke(ThreadContext * tc);
+    void invoke(ThreadContext * tc,
+            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
 #endif
 };
 

diff --git a/src/arch/sparc/nativetrace.cc b/src/arch/sparc/nativetrace.cc
index 02d4f4dbf1382a7462dd65df989c478d303dd301..8a1eb7a58671e44f21cbdc63cb14da53a7da5f9d 100644 (file)
--- a/src/arch/sparc/nativetrace.cc
+++ b/src/arch/sparc/nativetrace.cc
@@ -33,6 +33,7 @@
 #include "arch/sparc/nativetrace.hh"
 #include "cpu/thread_context.hh"
 #include "params/SparcNativeTrace.hh"
+#include "sim/byteswap.hh"
 
 namespace Trace {
 

diff --git a/src/arch/sparc/remote_gdb.cc b/src/arch/sparc/remote_gdb.cc
index 615c5b55168da8d6424b2bc4394fb7da892e64cb..4eea0c0774e6acc5412e440d038158e85130ca80 100644 (file)
--- a/src/arch/sparc/remote_gdb.cc
+++ b/src/arch/sparc/remote_gdb.cc
@@ -133,6 +133,7 @@
 #include "mem/page_table.hh"
 #include "mem/physical.hh"
 #include "mem/port.hh"
+#include "sim/byteswap.hh"
 #include "sim/process.hh"
 #include "sim/system.hh"
 

diff --git a/src/arch/sparc/tlb.cc b/src/arch/sparc/tlb.cc
index 9d3b22657af6e7ebea61e6fb6c30ce673580919b..a27774e85b7a046c65a429e17f72896a9840c7a4 100644 (file)
--- a/src/arch/sparc/tlb.cc
+++ b/src/arch/sparc/tlb.cc
@@ -31,6 +31,7 @@
 #include <cstring>
 
 #include "arch/sparc/asi.hh"
+#include "arch/sparc/faults.hh"
 #include "arch/sparc/registers.hh"
 #include "arch/sparc/tlb.hh"
 #include "base/bitfield.hh"

diff --git a/src/arch/sparc/tlb.hh b/src/arch/sparc/tlb.hh
index 76b6870421943d394345213bf61694f104e3c221..f63785de8bfbcedf4273377ecaf0c8c1fc678b4b 100644 (file)
--- a/src/arch/sparc/tlb.hh
+++ b/src/arch/sparc/tlb.hh
@@ -37,7 +37,7 @@
 #include "config/full_system.hh"
 #include "mem/request.hh"
 #include "params/SparcTLB.hh"
-#include "sim/faults.hh"
+#include "sim/fault.hh"
 #include "sim/tlb.hh"
 
 class ThreadContext;

diff --git a/src/arch/sparc/utility.cc b/src/arch/sparc/utility.cc
index 84e700f6d177b62a20c084e2fb63fef09b8f1f3c..9a062e841ac664d32d2efd3f8db6cf34fe469049 100644 (file)
--- a/src/arch/sparc/utility.cc
+++ b/src/arch/sparc/utility.cc
@@ -29,6 +29,7 @@
  *          Ali Saidi
  */
 
+#include "arch/sparc/faults.hh"
 #include "arch/sparc/utility.hh"
 #if FULL_SYSTEM
 #include "arch/sparc/vtophys.hh"
@@ -216,4 +217,13 @@ copyRegs(ThreadContext *src, ThreadContext *dest)
     dest->setNextPC(src->readNextPC());
     dest->setNextNPC(src->readNextNPC());
 }
+
+void
+initCPU(ThreadContext *tc, int cpuId)
+{
+    static Fault por = new PowerOnReset();
+    if (cpuId == 0)
+        por->invoke(tc);
+}
+
 } //namespace SPARC_ISA

diff --git a/src/arch/sparc/utility.hh b/src/arch/sparc/utility.hh
index fe3082c5e6cc03af4714203b8eca4d33dd231ece..70044a6c2a1332fc3ad9ad7c1f5afae4b73736a3 100644 (file)
--- a/src/arch/sparc/utility.hh
+++ b/src/arch/sparc/utility.hh
@@ -31,13 +31,13 @@
 #ifndef __ARCH_SPARC_UTILITY_HH__
 #define __ARCH_SPARC_UTILITY_HH__
 
-#include "arch/sparc/faults.hh"
 #include "arch/sparc/isa_traits.hh"
 #include "arch/sparc/registers.hh"
 #include "arch/sparc/tlb.hh"
 #include "base/misc.hh"
 #include "base/bitfield.hh"
 #include "cpu/thread_context.hh"
+#include "sim/fault.hh"
 
 namespace SparcISA
 {
@@ -57,14 +57,7 @@ namespace SparcISA
     template <class TC>
     void zeroRegisters(TC *tc);
 
-    inline void
-    initCPU(ThreadContext *tc, int cpuId)
-    {
-        static Fault por = new PowerOnReset();
-        if (cpuId == 0)
-            por->invoke(tc);
-
-    }
+    void initCPU(ThreadContext *tc, int cpuId);
 
     inline void
     startupCPU(ThreadContext *tc, int cpuId)

diff --git a/src/arch/x86/faults.cc b/src/arch/x86/faults.cc
index 836a785675189d6f3567f72c5d7ae5a5e7aa0f89..4c8fb33c2ce191b51e68a06afd98a856082567d3 100644 (file)
--- a/src/arch/x86/faults.cc
+++ b/src/arch/x86/faults.cc
@@ -56,7 +56,7 @@
 namespace X86ISA
 {
 #if FULL_SYSTEM
-    void X86FaultBase::invoke(ThreadContext * tc)
+    void X86FaultBase::invoke(ThreadContext * tc, StaticInstPtr inst)
     {
         Addr pc = tc->readPC();
         DPRINTF(Faults, "RIP %#x: vector %d: %s\n", pc, vector, describe());
@@ -102,7 +102,7 @@ namespace X86ISA
         return ss.str();
     }
     
-    void X86Trap::invoke(ThreadContext * tc)
+    void X86Trap::invoke(ThreadContext * tc, StaticInstPtr inst)
     {
         X86FaultBase::invoke(tc);
         // This is the same as a fault, but it happens -after- the instruction.
@@ -111,12 +111,12 @@ namespace X86ISA
         tc->setNextNPC(tc->readNextNPC() + sizeof(MachInst));
     }
 
-    void X86Abort::invoke(ThreadContext * tc)
+    void X86Abort::invoke(ThreadContext * tc, StaticInstPtr inst)
     {
         panic("Abort exception!");
     }
 
-    void PageFault::invoke(ThreadContext * tc)
+    void PageFault::invoke(ThreadContext * tc, StaticInstPtr inst)
     {
         HandyM5Reg m5reg = tc->readMiscRegNoEffect(MISCREG_M5_REG);
         X86FaultBase::invoke(tc);
@@ -141,7 +141,7 @@ namespace X86ISA
     }
 
     void
-    InitInterrupt::invoke(ThreadContext *tc)
+    InitInterrupt::invoke(ThreadContext *tc, StaticInstPtr inst)
     {
         DPRINTF(Faults, "Init interrupt.\n");
         // The otherwise unmodified integer registers should be set to 0.
@@ -248,7 +248,7 @@ namespace X86ISA
     }
 
     void
-    StartupInterrupt::invoke(ThreadContext *tc)
+    StartupInterrupt::invoke(ThreadContext *tc, StaticInstPtr inst)
     {
         DPRINTF(Faults, "Startup interrupt with vector %#x.\n", vector);
         HandyM5Reg m5Reg = tc->readMiscReg(MISCREG_M5_REG);
@@ -270,7 +270,7 @@ namespace X86ISA
 #else
 
     void
-    PageFault::invoke(ThreadContext * tc)
+    PageFault::invoke(ThreadContext * tc, StaticInstPtr inst)
     {
         PageFaultErrorCode code = errorCode;
         const char *modeStr = "";

diff --git a/src/arch/x86/faults.hh b/src/arch/x86/faults.hh
index bf3b6c8de4e63a5bbf41c1cda67ff099ca101c5e..f98ef72e93273e49aa1200c94e6ee97c62c52a92 100644 (file)
--- a/src/arch/x86/faults.hh
+++ b/src/arch/x86/faults.hh
@@ -86,7 +86,8 @@ namespace X86ISA
         }
 
 #if FULL_SYSTEM
-        void invoke(ThreadContext * tc);
+        void invoke(ThreadContext * tc,
+                StaticInstPtr inst = StaticInst::nullStaticInstPtr);
 
         virtual std::string describe() const;
 #endif
@@ -114,7 +115,8 @@ namespace X86ISA
         {}
 
 #if FULL_SYSTEM
-        void invoke(ThreadContext * tc);
+        void invoke(ThreadContext * tc,
+                StaticInstPtr inst = StaticInst::nullStaticInstPtr);
 #endif
     };
 
@@ -128,7 +130,8 @@ namespace X86ISA
         {}
 
 #if FULL_SYSTEM
-        void invoke(ThreadContext * tc);
+        void invoke(ThreadContext * tc,
+                StaticInstPtr inst = StaticInst::nullStaticInstPtr);
 #endif
     };
 
@@ -150,7 +153,8 @@ namespace X86ISA
             return "unimplemented_micro";
         }
 
-        void invoke(ThreadContext * tc)
+        void invoke(ThreadContext * tc,
+                StaticInstPtr inst = StaticInst::nullStaticInstPtr)
         {
             panic("Unimplemented instruction!");
         }
@@ -327,7 +331,8 @@ namespace X86ISA
             errorCode = code;
         }
 
-        void invoke(ThreadContext * tc);
+        void invoke(ThreadContext * tc,
+                StaticInstPtr inst = StaticInst::nullStaticInstPtr);
 
 #if FULL_SYSTEM
         virtual std::string describe() const;
@@ -397,7 +402,8 @@ namespace X86ISA
             X86Interrupt("INIT Interrupt", "#INIT", _vector)
         {}
 
-        void invoke(ThreadContext * tc);
+        void invoke(ThreadContext * tc,
+                StaticInstPtr inst = StaticInst::nullStaticInstPtr);
     };
 
     class StartupInterrupt : public X86Interrupt
@@ -407,7 +413,8 @@ namespace X86ISA
             X86Interrupt("Startup Interrupt", "#SIPI", _vector)
         {}
 
-        void invoke(ThreadContext * tc);
+        void invoke(ThreadContext * tc,
+                StaticInstPtr inst = StaticInst::nullStaticInstPtr);
     };
 
     class SoftwareInterrupt : public X86Interrupt

diff --git a/src/arch/x86/insts/microldstop.hh b/src/arch/x86/insts/microldstop.hh
index 18771f9a63a96a3f3a1ce1c436d5290c7370b53f..5487655e26b287115782f3b8b3e0fa045ffbeb4d 100644 (file)
--- a/src/arch/x86/insts/microldstop.hh
+++ b/src/arch/x86/insts/microldstop.hh
@@ -43,6 +43,7 @@
 #include "arch/x86/insts/microop.hh"
 #include "mem/packet.hh"
 #include "mem/request.hh"
+#include "sim/faults.hh"
 
 namespace X86ISA
 {

diff --git a/src/arch/x86/nativetrace.cc b/src/arch/x86/nativetrace.cc
index 3da2ecb1334a949cecf5ffd6b9603102318e38e6..c5c891be9f6aa5b75148429b1e9dd241ad33b181 100644 (file)
--- a/src/arch/x86/nativetrace.cc
+++ b/src/arch/x86/nativetrace.cc
@@ -34,6 +34,7 @@
 #include "arch/x86/regs/int.hh"
 #include "cpu/thread_context.hh"
 #include "params/X86NativeTrace.hh"
+#include "sim/byteswap.hh"
 
 namespace Trace {
 

diff --git a/src/arch/x86/tlb.hh b/src/arch/x86/tlb.hh
index 09a26f3e74572149a9e759a179749a51fecd2bc6..025418dc7f9aacaa5dc68121521a6a5110004636 100644 (file)
--- a/src/arch/x86/tlb.hh
+++ b/src/arch/x86/tlb.hh
@@ -50,7 +50,7 @@
 #include "mem/mem_object.hh"
 #include "mem/request.hh"
 #include "params/X86TLB.hh"
-#include "sim/faults.hh"
+#include "sim/fault.hh"
 #include "sim/tlb.hh"
 #include "sim/sim_object.hh"
 

diff --git a/src/base/types.hh b/src/base/types.hh
index 0c10fac64e1f15d384edd474a39224c9db809a03..30b2d9258a14d1a647bd617377bfbc65c97735b7 100644 (file)
--- a/src/base/types.hh
+++ b/src/base/types.hh
@@ -75,4 +75,8 @@ const Addr MaxAddr = (Addr)-1;
 typedef int16_t ThreadID;
 const ThreadID InvalidThreadID = (ThreadID)-1;
 
+class FaultBase;
+template <class T> class RefCountingPtr;
+typedef RefCountingPtr<FaultBase> Fault;
+
 #endif // __BASE_TYPES_HH__

diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh
index 41cb13949cedb244090707e7ee71b73f9dcafe14..e9b7daa4a03b068d3ebebce2958a400e01991ec7 100644 (file)
--- a/src/cpu/base_dyn_inst.hh
+++ b/src/cpu/base_dyn_inst.hh
@@ -49,6 +49,7 @@
 #include "cpu/static_inst.hh"
 #include "cpu/translation.hh"
 #include "mem/packet.hh"
+#include "sim/byteswap.hh"
 #include "sim/system.hh"
 #include "sim/tlb.hh"
 

diff --git a/src/cpu/checker/cpu_impl.hh b/src/cpu/checker/cpu_impl.hh
index 81f49463042416075550120a66ec04555009700e..494298cadab54fd365075fe4e8fe02c92050eb97 100644 (file)
--- a/src/cpu/checker/cpu_impl.hh
+++ b/src/cpu/checker/cpu_impl.hh
@@ -240,7 +240,7 @@ Checker<DynInstPtr>::verify(DynInstPtr &completed_inst)
 
         if (fault != NoFault) {
 #if FULL_SYSTEM
-            fault->invoke(tc);
+            fault->invoke(tc, curStaticInst);
             willChangePC = true;
             newPC = thread->readPC();
             DPRINTF(Checker, "Fault, PC is now %#x\n", newPC);

diff --git a/src/cpu/inorder/cpu.cc b/src/cpu/inorder/cpu.cc
index 059996b0723bc58b780ac1855fd64136975a4d90..5d4d3c5800be805a490d9d60f1763372017502ab 100644 (file)
--- a/src/cpu/inorder/cpu.cc
+++ b/src/cpu/inorder/cpu.cc
@@ -136,7 +136,7 @@ InOrderCPU::CPUEvent::process()
         break;
 
       case Trap:
-        cpu->trapCPU(fault, tid);
+        cpu->trapCPU(fault, tid, inst);
         break;
 
       default:
@@ -649,16 +649,16 @@ InOrderCPU::updateMemPorts()
 #endif
 
 void
-InOrderCPU::trap(Fault fault, ThreadID tid, int delay)
+InOrderCPU::trap(Fault fault, ThreadID tid, DynInstPtr inst, int delay)
 {
     //@ Squash Pipeline during TRAP
-    scheduleCpuEvent(Trap, fault, tid, dummyInst[tid], delay);
+    scheduleCpuEvent(Trap, fault, tid, inst, delay);
 }
 
 void
-InOrderCPU::trapCPU(Fault fault, ThreadID tid)
+InOrderCPU::trapCPU(Fault fault, ThreadID tid, DynInstPtr inst)
 {
-    fault->invoke(tcBase(tid));
+    fault->invoke(tcBase(tid), inst->staticInst);
 }
 
 void 

diff --git a/src/cpu/inorder/cpu.hh b/src/cpu/inorder/cpu.hh
index 450829e6416d40f2e13c638c996aae94d524270d..abe24d6ed927452bc31df2a15dacbf861f680d64 100644 (file)
--- a/src/cpu/inorder/cpu.hh
+++ b/src/cpu/inorder/cpu.hh
@@ -347,8 +347,8 @@ class InOrderCPU : public BaseCPU
     /** trap() - sets up a trap event on the cpuTraps to handle given fault.
      *  trapCPU() - Traps to handle given fault
      */
-    void trap(Fault fault, ThreadID tid, int delay = 0);
-    void trapCPU(Fault fault, ThreadID tid);
+    void trap(Fault fault, ThreadID tid, DynInstPtr inst, int delay = 0);
+    void trapCPU(Fault fault, ThreadID tid, DynInstPtr inst);
 
     /** Add Thread to Active Threads List. */
     void activateContext(ThreadID tid, int delay = 0);

diff --git a/src/cpu/inorder/inorder_dyn_inst.cc b/src/cpu/inorder/inorder_dyn_inst.cc
index 5486dedee1104b633e9c2c5bca5fd3c4401578c5..2465744e508fec0346b8d34323c77b832a0284f4 100644 (file)
--- a/src/cpu/inorder/inorder_dyn_inst.cc
+++ b/src/cpu/inorder/inorder_dyn_inst.cc
@@ -326,7 +326,7 @@ InOrderDynInst::hwrei()
 void
 InOrderDynInst::trap(Fault fault)
 {
-    this->cpu->trap(fault, this->threadNumber);
+    this->cpu->trap(fault, this->threadNumber, this);
 }
 
 

diff --git a/src/cpu/inorder/resources/cache_unit.cc b/src/cpu/inorder/resources/cache_unit.cc
index 67ee517435599e37bb85da5910e737ba375a9877..73deacb12a98b6a7dd872162778d9d9c2f1ae521 100644 (file)
--- a/src/cpu/inorder/resources/cache_unit.cc
+++ b/src/cpu/inorder/resources/cache_unit.cc
@@ -434,7 +434,7 @@ CacheUnit::doTLBAccess(DynInstPtr inst, CacheReqPtr cache_req, int acc_size,
 
         scheduleEvent(slot_idx, 1);
 
-        cpu->trap(cache_req->fault, tid);
+        cpu->trap(cache_req->fault, tid, inst);
     } else {
         DPRINTF(InOrderTLB, "[tid:%i]: [sn:%i] virt. addr %08p translated "
                 "to phys. addr:%08p.\n", tid, inst->seqNum,

diff --git a/src/cpu/inorder/resources/execution_unit.cc b/src/cpu/inorder/resources/execution_unit.cc
index 49ea329cd32ebe53995d4e350344bada673a467b..91e788fbc75166c350239efa14631027601d56d3 100644 (file)
--- a/src/cpu/inorder/resources/execution_unit.cc
+++ b/src/cpu/inorder/resources/execution_unit.cc
@@ -236,7 +236,7 @@ ExecutionUnit::execute(int slot_num)
                 } else {
                     warn("inst [sn:%i] had a %s fault",
                          seq_num, fault->name());
-                    cpu->trap(fault, tid);
+                    cpu->trap(fault, tid, inst);
                 }
             }
         }

diff --git a/src/cpu/inorder/resources/mult_div_unit.cc b/src/cpu/inorder/resources/mult_div_unit.cc
index 81e42b2b69ca2bffc1db9316f840c1c3bcb179a9..d9a887571192d3c5ba2bf2827126b074afc9d92f 100644 (file)
--- a/src/cpu/inorder/resources/mult_div_unit.cc
+++ b/src/cpu/inorder/resources/mult_div_unit.cc
@@ -301,7 +301,7 @@ MultDivUnit::exeMulDiv(int slot_num)
                 inst->readTid(), inst->readIntResult(0));
     } else {
         warn("inst [sn:%i] had a %s fault", seq_num, fault->name());
-        cpu->trap(fault, tid);
+        cpu->trap(fault, tid, inst);
     }    
 }
 

diff --git a/src/cpu/inorder/resources/tlb_unit.cc b/src/cpu/inorder/resources/tlb_unit.cc
index 0410d6b24ffffd2559546ecd45d6f59d3c29e7bb..59840d15bb55c49afb3bd19626a5730ad51401d5 100644 (file)
--- a/src/cpu/inorder/resources/tlb_unit.cc
+++ b/src/cpu/inorder/resources/tlb_unit.cc
@@ -176,7 +176,7 @@ TLBUnit::execute(int slot_idx)
                     scheduleEvent(slot_idx, 1);
 
                     // Let CPU handle the fault
-                    cpu->trap(tlb_req->fault, tid);
+                    cpu->trap(tlb_req->fault, tid, inst);
                 }
             } else {
                 DPRINTF(InOrderTLB, "[tid:%i]: [sn:%i] virt. addr %08p translated "

diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh
index cb5f2381443dc388d589eab1a29e476ca1e76814..468781e4d3326e92d00d368bc5b2e4fff39af726 100644 (file)
--- a/src/cpu/o3/commit_impl.hh
+++ b/src/cpu/o3/commit_impl.hh
@@ -1068,7 +1068,7 @@ DefaultCommit<Impl>::commitHead(DynInstPtr &head_inst, unsigned inst_num)
         // needed to update the state as soon as possible.  This
         // prevents external agents from changing any specific state
         // that the trap need.
-        cpu->trap(inst_fault, tid);
+        cpu->trap(inst_fault, tid, head_inst);
 
         // Exit state update mode to avoid accidental updating.
         thread[tid]->inSyscall = false;

diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index 49bfe88e343beda774eac83d56bc217b94437602..7eea04ce6469096a7334c96ce27288fe519e3336 100644 (file)
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -926,7 +926,8 @@ FullO3CPU<Impl>::processInterrupts(Fault interrupt)
     this->interrupts->updateIntrInfo(this->threadContexts[0]);
 
     DPRINTF(O3CPU, "Interrupt %s being handled\n", interrupt->name());
-    this->trap(interrupt, 0);
+    DynInstPtr dummyInst;
+    this->trap(interrupt, 0, dummyInst);
 }
 
 template <class Impl>
@@ -943,10 +944,10 @@ FullO3CPU<Impl>::updateMemPorts()
 
 template <class Impl>
 void
-FullO3CPU<Impl>::trap(Fault fault, ThreadID tid)
+FullO3CPU<Impl>::trap(Fault fault, ThreadID tid, DynInstPtr inst)
 {
     // Pass the thread's TC into the invoke method.
-    fault->invoke(this->threadContexts[tid]);
+    fault->invoke(this->threadContexts[tid], inst->staticInst);
 }
 
 #if !FULL_SYSTEM

diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh
index a102a21f53239779ff52e0d83f2ac5f635e62741..e7368993be70799be6679b6f8ccde5b0ddfbf7a2 100644 (file)
--- a/src/cpu/o3/cpu.hh
+++ b/src/cpu/o3/cpu.hh
@@ -367,7 +367,7 @@ class FullO3CPU : public BaseO3CPU
     { return globalSeqNum++; }
 
     /** Traps to handle given fault. */
-    void trap(Fault fault, ThreadID tid);
+    void trap(Fault fault, ThreadID tid, DynInstPtr inst);
 
 #if FULL_SYSTEM
     /** HW return from error interrupt. */

diff --git a/src/cpu/o3/dyn_inst_impl.hh b/src/cpu/o3/dyn_inst_impl.hh
index 8d391ceaffc79bd62c6266ddc1bfe5ba05c68ad3..9406e2be0b3a153aa58c9ff562e3cf5b0541404d 100644 (file)
--- a/src/cpu/o3/dyn_inst_impl.hh
+++ b/src/cpu/o3/dyn_inst_impl.hh
@@ -155,7 +155,7 @@ template <class Impl>
 void
 BaseO3DynInst<Impl>::trap(Fault fault)
 {
-    this->cpu->trap(fault, this->threadNumber);
+    this->cpu->trap(fault, this->threadNumber, this);
 }
 
 template <class Impl>

diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index 1726db1937e09590baa85e0118fb97e08c95df3e..d97e7aeecf4791cce2f8b6c8ab354ff249f15e83 100644 (file)
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -38,6 +38,7 @@
 #include "mem/packet.hh"
 #include "mem/packet_access.hh"
 #include "params/AtomicSimpleCPU.hh"
+#include "sim/faults.hh"
 #include "sim/system.hh"
 
 using namespace std;

diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index d7fc81de6ad8f8181c1d53694a566a4567c94a08..98feb8bf5560e1db948ca3933d728ebfc1d0614a 100644 (file)
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -506,7 +506,7 @@ BaseSimpleCPU::advancePC(Fault fault)
     fetchOffset = 0;
     if (fault != NoFault) {
         curMacroStaticInst = StaticInst::nullStaticInstPtr;
-        fault->invoke(tc);
+        fault->invoke(tc, curStaticInst);
         predecoder.reset();
     } else {
         //If we're at the last micro op for this instruction

diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index 4b093e115aeed621fd7ac869176e287bf005f948..7b45822d6b25f20d28930a511d35545f3bb6c807 100644 (file)
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -38,6 +38,7 @@
 #include "mem/packet.hh"
 #include "mem/packet_access.hh"
 #include "params/TimingSimpleCPU.hh"
+#include "sim/faults.hh"
 #include "sim/system.hh"
 
 using namespace std;

diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh
index 1fbb2ab5a7b0718b6c3b988d329be39db781efab..e4a7b7a77ed1190669ad9e6dc8257425facee4a7 100644 (file)
--- a/src/cpu/simple_thread.hh
+++ b/src/cpu/simple_thread.hh
@@ -241,13 +241,6 @@ class SimpleThread : public ThreadState
 
     virtual bool misspeculating();
 
-    Fault instRead(RequestPtr &req)
-    {
-        panic("instRead not implemented");
-        // return funcPhysMem->read(req, inst);
-        return NoFault;
-    }
-
     void copyArchRegs(ThreadContext *tc);
 
     void clearArchRegs()

diff --git a/src/cpu/static_inst.hh b/src/cpu/static_inst.hh
index fa42058364e8ac376254d3d88fb3ee168cd9b827..0ae8653c5d168a91bd3942b74edee30543bb06b8 100644 (file)
--- a/src/cpu/static_inst.hh
+++ b/src/cpu/static_inst.hh
@@ -43,8 +43,7 @@
 #include "base/refcnt.hh"
 #include "base/types.hh"
 #include "cpu/op_class.hh"
-#include "sim/faults.hh"
-#include "sim/faults.hh"
+#include "sim/fault.hh"
 
 // forward declarations
 struct AlphaSimpleImpl;

diff --git a/src/cpu/thread_context.hh b/src/cpu/thread_context.hh
index 7f6d258abcb45a2625471a29df0d674e52ddeb2c..84ef579225e3629c6ca2c0758ec2d8e0b25963f3 100644 (file)
--- a/src/cpu/thread_context.hh
+++ b/src/cpu/thread_context.hh
@@ -36,9 +36,6 @@
 #include "base/types.hh"
 #include "config/full_system.hh"
 #include "config/the_isa.hh"
-#include "mem/request.hh"
-#include "sim/byteswap.hh"
-#include "sim/faults.hh"
 #include "sim/serialize.hh"
 
 // @todo: Figure out a more architecture independent way to obtain the ITB and

diff --git a/src/cpu/translation.hh b/src/cpu/translation.hh
index 983a748cfadcb5c2f4482547882ee7345042922e..7db7c381aacc6299aabae309337f9001f13c23f7 100644 (file)
--- a/src/cpu/translation.hh
+++ b/src/cpu/translation.hh
@@ -33,6 +33,7 @@
 #ifndef __CPU_TRANSLATION_HH__
 #define __CPU_TRANSLATION_HH__
 
+#include "sim/faults.hh"
 #include "sim/tlb.hh"
 
 /**

diff --git a/src/kern/kernel_stats.hh b/src/kern/kernel_stats.hh
index 85a47ec0007993471dfe109368974945f83978aa..cd3c12d47602bfdb4c992be823dc37dc608ab440 100644 (file)
--- a/src/kern/kernel_stats.hh
+++ b/src/kern/kernel_stats.hh
@@ -35,6 +35,7 @@
 #include <string>
 
 #include "cpu/static_inst.hh"
+#include "sim/stats.hh"
 #include "sim/serialize.hh"
 
 class BaseCPU;

diff --git a/src/kern/tru64/tru64.hh b/src/kern/tru64/tru64.hh
index d0c11a9343022999e242c35f112f254698d12456..d3348fe89617a12a1b9b68e858923cd406624620 100644 (file)
--- a/src/kern/tru64/tru64.hh
+++ b/src/kern/tru64/tru64.hh
@@ -34,6 +34,7 @@
 
 #include "config/full_system.hh"
 #include "kern/operatingsystem.hh"
+#include "sim/byteswap.hh"
 
 #if FULL_SYSTEM
 

diff --git a/src/mem/page_table.cc b/src/mem/page_table.cc
index bcaf5582a2f1f113cca2f163a5c85dcb973ab38c..7e6eac372f295eb1e0da3deed6867d6939518dc2 100644 (file)
--- a/src/mem/page_table.cc
+++ b/src/mem/page_table.cc
@@ -38,12 +38,12 @@
 #include <map>
 #include <fstream>
 
-#include "arch/faults.hh"
 #include "base/bitfield.hh"
 #include "base/intmath.hh"
 #include "base/trace.hh"
 #include "config/the_isa.hh"
 #include "mem/page_table.hh"
+#include "sim/faults.hh"
 #include "sim/process.hh"
 #include "sim/sim_object.hh"
 #include "sim/system.hh"

diff --git a/src/mem/page_table.hh b/src/mem/page_table.hh
index 0d93d37c78070606138a37c3509bdcb6c138255c..61da5f322a57d9119c54cec19bc6ddb21c46f0aa 100644 (file)
--- a/src/mem/page_table.hh
+++ b/src/mem/page_table.hh
@@ -44,7 +44,6 @@
 #include "base/types.hh"
 #include "config/the_isa.hh"
 #include "mem/request.hh"
-#include "sim/faults.hh"
 #include "sim/serialize.hh"
 
 class Process;

diff --git a/src/sim/fault.hh b/src/sim/fault.hh
new file mode 100644 (file)
index 0000000..ac0b691
--- /dev/null
+++ b/src/sim/fault.hh
@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) 2010 Advanced Micro Devices
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Gabe Black
+ */
+
+#ifndef __SIM_FAULT_HH__
+#define __SIM_FAULT_HH__
+
+class FaultBase;
+template <class T> class RefCountingPtr;
+typedef RefCountingPtr<FaultBase> Fault;
+
+#endif // __SIM_FAULT_HH__

diff --git a/src/sim/faults.cc b/src/sim/faults.cc
index 10f0b9a66456db148d3e15ecfc7030a21e698d41..78b9fb0a49d3608152e0110acaf565e8990a8bd9 100644 (file)
--- a/src/sim/faults.cc
+++ b/src/sim/faults.cc
@@ -38,12 +38,12 @@
 #include "mem/page_table.hh"
 
 #if !FULL_SYSTEM
-void FaultBase::invoke(ThreadContext * tc)
+void FaultBase::invoke(ThreadContext * tc, StaticInstPtr inst)
 {
     panic("fault (%s) detected @ PC %p", name(), tc->readPC());
 }
 #else
-void FaultBase::invoke(ThreadContext * tc)
+void FaultBase::invoke(ThreadContext * tc, StaticInstPtr inst)
 {
     DPRINTF(Fault, "Fault %s at PC: %#x\n", name(), tc->readPC());
 
@@ -51,13 +51,13 @@ void FaultBase::invoke(ThreadContext * tc)
 }
 #endif
 
-void UnimpFault::invoke(ThreadContext * tc)
+void UnimpFault::invoke(ThreadContext * tc, StaticInstPtr inst)
 {
     panic("Unimpfault: %s\n", panicStr.c_str());
 }
 
 #if !FULL_SYSTEM
-void GenericPageTableFault::invoke(ThreadContext *tc)
+void GenericPageTableFault::invoke(ThreadContext *tc, StaticInstPtr inst)
 {
     Process *p = tc->getProcessPtr();
 
@@ -66,7 +66,7 @@ void GenericPageTableFault::invoke(ThreadContext *tc)
 
 }
 
-void GenericAlignmentFault::invoke(ThreadContext *tc)
+void GenericAlignmentFault::invoke(ThreadContext *tc, StaticInstPtr inst)
 {
     panic("Alignment fault when accessing virtual address %#x\n", vaddr);
 }

diff --git a/src/sim/faults.hh b/src/sim/faults.hh
index f2fa30b60f971531574c8491224b13b8e6f9bed5..e48928b2c8540d5991e9b010290cbf0f734327fe 100644 (file)
--- a/src/sim/faults.hh
+++ b/src/sim/faults.hh
@@ -33,12 +33,13 @@
 #define __FAULTS_HH__
 
 #include "base/refcnt.hh"
+#include "base/types.hh"
+#include "sim/fault.hh"
 #include "sim/stats.hh"
 #include "config/full_system.hh"
+#include "cpu/static_inst.hh"
 
 class ThreadContext;
-class FaultBase;
-typedef RefCountingPtr<FaultBase> Fault;
 
 typedef const char * FaultName;
 typedef Stats::Scalar FaultStat;
@@ -54,7 +55,8 @@ class FaultBase : public RefCounted
 {
   public:
     virtual FaultName name() const = 0;
-    virtual void invoke(ThreadContext * tc);
+    virtual void invoke(ThreadContext * tc,
+            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
     virtual bool isMachineCheckFault() const {return false;}
     virtual bool isAlignmentFault() const {return false;}
 };
@@ -71,7 +73,8 @@ class UnimpFault : public FaultBase
     { }
 
     FaultName name() const {return "Unimplemented simulator feature";}
-    void invoke(ThreadContext * tc);
+    void invoke(ThreadContext * tc,
+            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
 };
 
 #if !FULL_SYSTEM
@@ -82,7 +85,8 @@ class GenericPageTableFault : public FaultBase
   public:
     FaultName name() const {return "Generic page table fault";}
     GenericPageTableFault(Addr va) : vaddr(va) {}
-    void invoke(ThreadContext * tc);
+    void invoke(ThreadContext * tc,
+            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
 };
 
 class GenericAlignmentFault : public FaultBase
@@ -92,7 +96,8 @@ class GenericAlignmentFault : public FaultBase
   public:
     FaultName name() const {return "Generic alignment fault";}
     GenericAlignmentFault(Addr va) : vaddr(va) {}
-    void invoke(ThreadContext * tc);
+    void invoke(ThreadContext * tc,
+            StaticInstPtr inst = StaticInst::nullStaticInstPtr);
 };
 #endif
 

diff --git a/src/sim/process_impl.hh b/src/sim/process_impl.hh
index 9d12113d0df088c4f31505b0ef39a3e3e3fb892f..1db533428b92fb81fa7885f730a89b99b7cdadfd 100644 (file)
--- a/src/sim/process_impl.hh
+++ b/src/sim/process_impl.hh
@@ -45,6 +45,7 @@
 #include <vector>
 
 #include "mem/translating_port.hh"
+#include "sim/byteswap.hh"
 
 
 //This needs to be templated for cases where 32 bit pointers are needed.

diff --git a/src/sim/syscall_emul.hh b/src/sim/syscall_emul.hh
index 703bbd1e0e1a194e54f7030521343dc09b7ed517..eaec57ef53628d5e72a724b251a4c3a0d96d964b 100644 (file)
--- a/src/sim/syscall_emul.hh
+++ b/src/sim/syscall_emul.hh
@@ -62,6 +62,7 @@
 #include "cpu/thread_context.hh"
 #include "mem/translating_port.hh"
 #include "mem/page_table.hh"
+#include "sim/byteswap.hh"
 #include "sim/system.hh"
 #include "sim/process.hh"
 

diff --git a/src/sim/tlb.cc b/src/sim/tlb.cc
index e9a719ffa6cb53f3dee5ff297a2661b47e55a66b..e2f4f9135ebbdc1bc1df1afb56b0c1787908373c 100644 (file)
--- a/src/sim/tlb.cc
+++ b/src/sim/tlb.cc
@@ -31,6 +31,7 @@
 #include "cpu/thread_context.hh"
 #include "mem/page_table.hh"
 #include "sim/process.hh"
+#include "sim/faults.hh"
 #include "sim/tlb.hh"
 
 Fault

diff --git a/src/sim/tlb.hh b/src/sim/tlb.hh
index db62b691def102cf641cfe9e655be2cc953fba40..ddd3127e50987a1c7666f7647b6db11b2615620c 100644 (file)
--- a/src/sim/tlb.hh
+++ b/src/sim/tlb.hh
@@ -33,7 +33,7 @@
 
 #include "base/misc.hh"
 #include "mem/request.hh"
-#include "sim/faults.hh"
+#include "sim/fault.hh"
 #include "sim/sim_object.hh"
 
 class ThreadContext;