(ext shift patterns): No longer needed.

From-SVN: r2427

diff --git a/gcc/config/m88k/m88k.md b/gcc/config/m88k/m88k.md
index d559474ab76014e72ffef42c47f86174267a74e4..2e26800e1a3cfc3e3eae149f5333dec26611626e 100644 (file)
--- a/gcc/config/m88k/m88k.md
+++ b/gcc/config/m88k/m88k.md
@@ -28,7 +28,7 @@
 (define_expand "m88k_sccs_id"
   [(match_operand:SI 0 "" "")]
   ""
-  "{ static char sccs_id[] = \"@(#)m88k.md     2.2.13.2 10/09/92 13:24:17\";
+  "{ static char sccs_id[] = \"@(#)m88k.md     2.2.13.3 10/13/92 13:03:43\";
      FAIL; }")
 \f
 ;; Attribute specifications
@@ -329,37 +329,6 @@
 ;; produce the necessary insns to support TARGET_*_LARGE_SHIFT, so nothing
 ;; special needs to be done here.
 
-;; (a << int1) >> int2 optimizations into a single extract.
-;; These patterns need to occur before the normal shift patterns
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r")
-       (ashiftrt:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
-                               (match_operand:SI 2 "int5_operand" ""))
-                    (match_operand:SI 3 "int5_operand" "")))]
-  "INTVAL (operands [2]) <= INTVAL (operands [3])"
-  "*
-{
-  operands[4] = gen_rtx (CONST_INT, SImode,
-                        INTVAL (operands[3]) - INTVAL (operands[2]));
-  return \"ext %0,%1,%w3<%4>\";  /* <(%3-%2)> */
-}"
-  [(set_attr "type" "bit")])
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r")
-       (lshiftrt:SI (ashift:SI (match_operand:SI 1 "register_operand" "r")
-                               (match_operand:SI 2 "int5_operand" ""))
-                    (match_operand:SI 3 "int5_operand" "")))]
-  "INTVAL (operands [2]) <= INTVAL (operands [3])"
-  "*
-{
-  operands[4] = gen_rtx (CONST_INT, SImode,
-                        INTVAL (operands[3]) - INTVAL (operands[2]));
-  return \"extu %0,%1,%w3<%4>\";  /* <(%3-%2)> */
-}"
-  [(set_attr "type" "bit")])
-
 ;; Optimize possible cases of the set instruction.
 
 (define_insn ""