fhdl: support memory read enable

diff --git a/examples/memory.py b/examples/memory.py
index e8f4531e6407644abf33fd2726115b556ed2ed10..ec61c83a981431b1a18fa97aa491721f4bee7857 100644 (file)
--- a/examples/memory.py
+++ b/examples/memory.py
@@ -9,13 +9,15 @@ a1 = Signal(BV(d_b))
 d1 = Signal(BV(w))
 we1 = Signal(BV(4))
 dw1 = Signal(BV(w))
-p1 = MemoryPort(a1, d1, we1, dw1, we_granularity=8, mode=WRITE_FIRST)
+re = Signal()
+p1 = MemoryPort(a1, d1, we1, dw1, we_granularity=8)
 
 a2 = Signal(BV(d_b))
 d2 = Signal(BV(w))
-p2 = MemoryPort(a2, d2)
+re2 = Signal()
+p2 = MemoryPort(a2, d2, re=re2)
 
 mem = Memory(w, d, p1, p2, init=[5, 18, 32])
 f = Fragment(memories=[mem])
-v = verilog.convert(f, ios={a1, d1, we1, dw1, a2, d2})
+v = verilog.convert(f, ios={a1, d1, we1, dw1, a2, d2, re2})
 print(v)

diff --git a/migen/fhdl/verilog_mem_behavioral.py b/migen/fhdl/verilog_mem_behavioral.py
index 31dddfa24a03f2fa4b5bdeabb85f7ca44e022bb4..bb3f437dcfa9c68ccb07bbf07eb116f5657b9426 100644 (file)
--- a/migen/fhdl/verilog_mem_behavioral.py
+++ b/migen/fhdl/verilog_mem_behavioral.py
@@ -41,14 +41,19 @@ def handler(memory, ns, clk):
                                r += "\t\t" + gn(storage) + "[" + gn(port.adr) + "] <= " + gn(port.dat_w) + ";\n"
                if not port.async_read:
                        if port.mode == WRITE_FIRST and port.we is not None:
-                               r += "\t" + gn(adr_regs[id(port)]) + " <= " + gn(port.adr) + ";\n"
+                               rd = "\t" + gn(adr_regs[id(port)]) + " <= " + gn(port.adr) + ";\n"
                        else:
                                bassign = gn(data_regs[id(port)]) + " <= " + gn(storage) + "[" + gn(port.adr) + "];\n"
                                if port.mode == READ_FIRST or port.we is None:
-                                       r += "\t" + bassign
+                                       rd = "\t" + bassign
                                elif port.mode == NO_CHANGE:
-                                       r += "\tif (!" + gn(port.we) + ")\n"
-                                       r += "\t\t" + bassign
+                                       rd = "\tif (!" + gn(port.we) + ")\n" \
+                                         + "\t\t" + bassign
+               if port.re is None:
+                       r += rd
+               else:
+                       r += "\tif (" + gn(port.re) + ")\n"
+                       r += "\t" + rd.replace("\n\t", "\n\t\t")
        r += "end\n\n"
        
        for port in memory.ports: