pysvp64asm: make zz also set src_zero

diff --git a/src/openpower/sv/trans/svp64.py b/src/openpower/sv/trans/svp64.py
index dda0576c21ed5dd6a24c8506b94a16b9d6285865..40fdc0effdd09b540f97d54e3372eff475a62bad 100644 (file)
--- a/src/openpower/sv/trans/svp64.py
+++ b/src/openpower/sv/trans/svp64.py
@@ -1113,6 +1113,7 @@ class SVP64Asm:
             # predicate zeroing
             elif encmode == 'zz': # TODO, a lot more checking on legality
                 dst_zero = 1      # NOT on cr_ops, that's RM[6]
+                src_zero = 1
             elif encmode == 'sz':
                 src_zero = 1
             elif encmode == 'dz':