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diff --git a/nlnet_2023_simplev_riscv.mdwn b/nlnet_2023_simplev_riscv.mdwn
index 40b4c8fc5b4ef068f8525e054e31bdfc61cbd9e5..36ecc7d4b8e061fb08ebe6b5bc6627fcaac86e9a 100644 (file)
--- a/nlnet_2023_simplev_riscv.mdwn
+++ b/nlnet_2023_simplev_riscv.mdwn
@@ -35,7 +35,7 @@ RISC-V is the largest open-source global community for microprocessor architectu
 
 # Have you been involved with projects or organisations relevant to this project before? And if so, can you tell us a bit about your contributions?
 
-A sequence of projects has enabled early development of vectorisation techniques in the RISC-V domain, and higher performance demonstration with OpenPOWER ISA. This project takes the learnings from previous projects to create a powerful RISC-V based vector ISA capable of the performance of POWER. A full project list is maintained at: <https://libre-soc.org/nlnet_proposals/>
+A sequence of projects has enabled early development of vectorisation techniques in the RISC-V domain, and higher performance demonstration with OpenPOWER ISA. This project takes the learnings from previous projects to create a powerful RISC-V based vector ISA capable of the performance of the Power ISA. A full project list is maintained at: <https://libre-soc.org/nlnet_proposals/>
 they include recently:
 
 * <https://libre-soc.org/nlnet_2022_opf_isa_wg/> - improving SVP64