(no commit message)

diff --git a/openpower/sv/svp_rewrite/svp64.mdwn b/openpower/sv/svp_rewrite/svp64.mdwn
index f20be688ddd715319af350417cbd257f6a3990a0..6358b5e1ec7b602d2be7151d38df17500de4e934 100644 (file)
--- a/openpower/sv/svp_rewrite/svp64.mdwn
+++ b/openpower/sv/svp_rewrite/svp64.mdwn
@@ -43,7 +43,7 @@ detrimental adverse effect.
 Consequently in SV, XER.SO and CR.OV behaviour is disregarded.  XER is
 simply neither read nor written.  This includes when `scalar identity behaviour` occurs.  If OpenPOWER v3.0/1 scalar behaviour is desired then OpenPOWER v3.0/1 instructions should be used, not SV Prefixed ones.
 
-# Register Naming
+# Register Naming and size
 
 SV Registers are simply the INT, FP and CR register files extended
 linearly to larger sizes; SV Vectorisation iterates sequentially through these registers.
@@ -64,6 +64,11 @@ i.e. under these circumstances (EXTRA=0) the register field names RA,
 RB etc. are interpreted and treated as v3.0B / v3.1B scalar registers.  This is part of
 `scalar identity behaviour` described above.
 
+## Future expansion.
+
+With the way that EXTRA fields are defined and applied to register fields,
+future versions of SV may involve 256 or greater registers.  To accommodate 256 registers, numbering of Vectors will simply shift up by one bit.  Backwards bibary compatibility may be achieved with a PCR bit.  Beyond this, further discussion is out of scope for this version of svp64.
+
 # Remapped Encoding (`RM[0:23]`)
 
 To allow relatively easy remapping of which portions of the Prefix Opcode