hdl.dsl: add missing case width check for Enum values.

Fixes #305.

diff --git a/nmigen/hdl/dsl.py b/nmigen/hdl/dsl.py
index 07c0a1b8e905883a8ac48ff58047220bd259b15b..b8f7692ec63454279cab8af96849e378c2d8ec68 100644 (file)
--- a/nmigen/hdl/dsl.py
+++ b/nmigen/hdl/dsl.py
@@ -309,6 +309,13 @@ class Module(_ModuleBuilderRoot, Elaboratable):
                               .format(pattern, len(switch_data["test"])),
                               SyntaxWarning, stacklevel=3)
                 continue
+            if isinstance(pattern, Enum) and bits_for(pattern.value) > len(switch_data["test"]):
+                warnings.warn("Case pattern '{:b}' ({}.{}) is wider than switch value "
+                              "(which has width {}); comparison will never be true"
+                              .format(pattern.value, pattern.__class__.__name__, pattern.name,
+                                      len(switch_data["test"])),
+                              SyntaxWarning, stacklevel=3)
+                continue
             new_patterns = (*new_patterns, pattern)
         try:
             _outer_case, self._statements = self._statements, []

diff --git a/nmigen/test/test_hdl_dsl.py b/nmigen/test/test_hdl_dsl.py
index d590035fbdd788bb6653377ac3577fab63982f1f..1ef32fa3e6377e60625f6ebfd95a330d9c84ebc6 100644 (file)
--- a/nmigen/test/test_hdl_dsl.py
+++ b/nmigen/test/test_hdl_dsl.py
@@ -400,6 +400,8 @@ class DSLTestCase(FHDLTestCase):
         """)
 
     def test_Case_width_wrong(self):
+        class Color(Enum):
+            RED = 0b10101010
         m = Module()
         with m.Switch(self.w1):
             with self.assertRaises(SyntaxError,
@@ -411,6 +413,11 @@ class DSLTestCase(FHDLTestCase):
                         "comparison will never be true"):
                 with m.Case(0b10110):
                     pass
+            with self.assertWarns(SyntaxWarning,
+                    msg="Case pattern '10101010' (Color.RED) is wider than switch value "
+                        "(which has width 4); comparison will never be true"):
+                with m.Case(Color.RED):
+                    pass
         self.assertRepr(m._statements, """
         (
             (switch (sig w1) )