(no commit message)

diff --git a/conferences/ics2021.mdwn b/conferences/ics2021.mdwn
index 84d8f6f116978a2944721769f0b058016b66ec10..fc6c38dc48573ce7ff9868c6b39ba121e53afbac 100644 (file)
--- a/conferences/ics2021.mdwn
+++ b/conferences/ics2021.mdwn
@@ -43,9 +43,10 @@ Loops from DSPs and Intel MMX, the end result is something entirely new.
 This talk will go through the development process of SVP64 and explain
 some of the innovative Vectorisation concepts that have never been seen 
 before in any commercial or academic Vector ISA, including
-Twin-Predication and "Post-result" predication, and how these will
-benefit Supercomputing performance and decrease power consumption,
-by reducing I-Cache usage.
+Twin-Predication and Condition Register "Post-result" predication,
+and how these will benefit Supercomputing performance and decrease
+power consumption, most notably by reducing program size and
+thus I-Cache usage whilst still maintaining high data throughput.
 
 ## Comprehensive life-cycle of mixed testing: HDL to gates