Merge zizzer:/z/m5/Bitkeeper/newmem

into  zizzer.eecs.umich.edu:/.automount/zazzer/z/rdreslin/m5bk/newmem

src/python/m5/objects/BaseCPU.py:
    Merge duplicate change

--HG--
extra : convert_revision : 214e57999ee78aadfc86e1f0b7198ff0d981ce16

diff --combined src/mem/packet.hh
index 068fea678f6b85ef5d6b7f22edefbd2dce73b23d,a88c78a783553e22ae2d894e4a69ff41f7806789..5d8308df7715844378d6d432bc9c87113c9be5b0
--- 1/src/mem/packet.hh
--- 2/src/mem/packet.hh
+++ b/src/mem/packet.hh
@@@ -223,7 -223,7 +223,7 @@@ class Packe
      bool isNoAllocate() { return (flags & NO_ALLOCATE) != 0; }
      bool isCompressed() { return (flags & COMPRESSED) != 0; }
  
 -    bool nic_pkt() { assert("Unimplemented\n" && 0); }
 +    bool nic_pkt() { assert("Unimplemented\n" && 0); return false; }
  
      /** Possible results of a packet's request. */
      enum Result
@@@ -266,6 -266,7 +266,7 @@@
             result(Unknown)
      {
          flags = 0;
+         time = curTick;
      }
  
      /** Alternate constructor if you are trying to create a packet with
@@@ -280,6 -281,7 +281,7 @@@
             result(Unknown)
      {
          flags = 0;
+         time = curTick;
      }
  
      /** Destructor. */
@@@ -295,6 -297,7 +297,7 @@@
          assert(req->validPaddr);
          addr = req->paddr;
          size = req->size;
+         time = req->time;
          addrSizeValid = true;
          result = Unknown;
          if (dynamicData) {

diff --combined src/python/m5/objects/BaseCPU.py
index 81e09c94cac6246806a1a7dfc85f48f0ea44c379,88a8bf5e346d0318c2d9a916cd232d8be786e77f..41e90b12b9762f19fb4f2a8877c34e35f8bc9ae3
--- 1/src/python/m5/objects/BaseCPU.py
--- 2/src/python/m5/objects/BaseCPU.py
+++ b/src/python/m5/objects/BaseCPU.py
@@@ -6,7 -6,7 +6,7 @@@ from Bus import Bu
  class BaseCPU(SimObject):
      type = 'BaseCPU'
      abstract = True
 -    mem = Param.MemObject(Parent.any, "memory")
 +    mem = Param.MemObject("memory")
  
      system = Param.System(Parent.any, "system object")
      if build_env['FULL_SYSTEM']:
@@@ -43,6 -43,7 +43,7 @@@
          self.icache_port = ic.cpu_side
          self.dcache_port = dc.cpu_side
          self._mem_ports = ['icache.mem_side', 'dcache.mem_side']
+ #        self.mem = dc
  
      def addTwoLevelCacheHierarchy(self, ic, dc, l2c):
          self.addPrivateSplitL1Caches(ic, dc)

diff --combined tests/configs/simple-timing.py
index 9a5b20e88e818a87f4ebbfc801b19ab23eef6e4c,78dfabe3bd54f8be14d9e9bff52203f8e2548994..7bb76db0e498b8b337451d16ea10b4974d261e14
--- 1/tests/configs/simple-timing.py
--- 2/tests/configs/simple-timing.py
+++ b/tests/configs/simple-timing.py
@@@ -40,7 -40,6 +40,7 @@@ cpu = TimingSimpleCPU(
  cpu.addTwoLevelCacheHierarchy(MyCache(size = '128kB'), MyCache(size = '256kB'),
                                MyCache(size = '2MB'))
  cpu.mem = cpu.dcache
- 
++cpu.mem = cpu.dcache
  system = System(cpu = cpu,
                  physmem = PhysicalMemory(),
                  membus = Bus())