from openpower.simulator.program import Program
-from openpower.decoder.isa.all import ISA
from openpower.endian import bigendian
from openpower.consts import MSR
-
-
+from openpower.test.state import ExpectedState
from openpower.test.common import TestAccumulatorBase, skip_case
-import random
class SPRTestCase(TestAccumulatorBase):
initial_regs = [0] * 32
initial_sprs = {'SRR0': 0x12345678, 'SRR1': 0x5678, 'LR': 0x1234,
'XER': 0xe00c0000}
+ e = ExpectedState(pc=16)
+ e.intregs[1] = 0x12345678
+ e.intregs[2] = 0x5678
+ e.intregs[3] = 0x1234
+ e.intregs[4] = 0xe00c0000
+ e.so = 0x1
+ e.ov = 0x3
+ e.ca = 0x3
+ e.sprs['LR'] = 0x1234
+ e.sprs['SRR0'] = 0x12345678
+ e.sprs['SRR1'] = 0x5678
self.add_case(Program(lst, bigendian),
- initial_regs, initial_sprs)
+ initial_regs, initial_sprs, expected=e)
def case_1_mtspr(self):
lst = ["mtspr 26, 1", # SRR0
initial_regs[4] = 0x1010101010101010
initial_sprs = {'SRR0': 0x12345678, 'SRR1': 0x5678, 'LR': 0x1234,
'XER': 0x0}
+ e = ExpectedState(pc=16, int_regs=initial_regs)
+ e.so = 0x1
+ e.ov = 0x3
+ e.ca = 0x3
+ e.sprs['LR'] = 0x1234
+ e.sprs['CTR'] = 0x1010101010101010
+ e.sprs['SRR0'] = 0x129518230011feed
+ e.sprs['SRR1'] = 0x123518230011feed
self.add_case(Program(lst, bigendian),
- initial_regs, initial_sprs)
+ initial_regs, initial_sprs, expected=e)
def case_2_mtspr_mfspr(self):
lst = ["mtspr 26, 1", # SRR0
initial_regs[4] = 0x1010101010101010
initial_sprs = {'SRR0': 0x12345678, 'SRR1': 0x5678, 'LR': 0x1234,
'XER': 0x0}
+ e = ExpectedState(pc=32)
+ e.intregs[1] = 0x129518230011feed
+ e.intregs[2] = 0x129518230011feed
+ e.intregs[3] = 0x123518230011feed
+ e.intregs[4] = 0xe00c0000
+ e.intregs[5] = 0x1010101010101010
+ e.so = 0x1
+ e.ov = 0x3
+ e.ca = 0x3
+ e.sprs['LR'] = 0x1234
+ e.sprs['CTR'] = 0x1010101010101010
+ e.sprs['SRR0'] = 0x129518230011feed
+ e.sprs['SRR1'] = 0x123518230011feed
+ e.msr = 0x9000000000002903
self.add_case(Program(lst, bigendian),
- initial_regs, initial_sprs)
+ initial_regs, initial_sprs, expected=e)
# TODO XXX whoops...
- @skip_case("spr does not have TRAP in it. has to be done another way")
+ # @skip_case("spr does not have TRAP in it. has to be done another way")
def case_3_mtspr_priv(self):
lst = ["mtspr 26, 1", # SRR0
"mtspr 27, 2", # SRR1
initial_sprs = {'SRR0': 0x12345678, 'SRR1': 0x5678, 'LR': 0x1234,
'XER': 0x0}
msr = 1 << MSR.PR
+ e = ExpectedState(pc=0x700)
+ e.intregs[1] = 0x129518230011feed
+ e.intregs[2] = 0x123518230011feed
+ e.intregs[3] = 0xe00c0000
+ e.intregs[4] = 0x1010101010101010
+ e.sprs['LR'] = 0x1234
+ e.sprs['SRR1'] = 0x44000
+ e.msr = 0x8000000000000001
self.add_case(Program(lst, bigendian),
- initial_regs, initial_sprs, initial_msr=msr)
+ initial_regs, initial_sprs, initial_msr=msr, expected=e)
def case_4_mfspr_slow(self):
lst = ["mfspr 1, 272", # SPRG0
initial_regs = [0] * 32
initial_sprs = {'SPRG0_priv': 0x12345678, 'SPRG1_priv': 0x5678,
}
+ e = ExpectedState(pc=8)
+ e.intregs[1] = 0x12345678
+ e.intregs[4] = 0x5678
+ e.sprs['SPRG0_priv'] = 0x12345678
+ e.sprs['SPRG1_priv'] = 0x5678
self.add_case(Program(lst, bigendian),
- initial_regs, initial_sprs)
+ initial_regs, initial_sprs, expected=e)
def case_5_mtspr(self):
lst = ["mtspr 272, 1", # SPRG0
initial_regs[2] = 0x123518230011fee0
initial_sprs = {'SPRG0_priv': 0x12345678, 'SPRG1_priv': 0x5678,
}
+ e = ExpectedState(pc=8)
+ e.intregs[1] = 0x129518230011feed
+ e.intregs[2] = 0x123518230011fee0
+ e.sprs['SPRG0_priv'] = 0x129518230011feed
+ e.sprs['SPRG1_priv'] = 0x123518230011fee0
self.add_case(Program(lst, bigendian),
- initial_regs, initial_sprs)
+ initial_regs, initial_sprs, expected=e)
def case_6_set_tb(self):
lst = [ "mtspr 268, 2", # TB
initial_regs[2] = 0x123518230011fee0
initial_sprs = {'TB': 0x12345678,
}
+ # we can't expect a specific value of TB since
+ # it changes due to counting time
self.add_case(Program(lst, bigendian),
- initial_regs, initial_sprs)
+ initial_regs, initial_sprs, expected=None)