gas/

	* config/tc-aarch64.c (parse_operands): Handle AARCH64_OPND_COND1.

gas/testsuite/

	* gas/aarch64/alias.s: Add tests.
	* gas/aarch64/alias.d: Update.
	* gas/aarch64/no-aliases.d: Update.
	* gas/aarch64/diagnostic.s: Add tests.
	* gas/aarch64/diagnostic.l: Update.
	* gas/aarch64/illegal.s: Add tests.
	* gas/aarch64/illegal.l: Update.

include/opcode/

	* aarch64.h (enum aarch64_operand_class): Add AARCH64_OPND_CLASS_COND.
	(enum aarch64_opnd): Add AARCH64_OPND_COND1.

opcodes/

	* aarch64-dis.c (convert_ubfm_to_lsl): Check for cond != '111x'.
	(convert_from_csel): Likewise.
	* aarch64-opc.c (operand_general_constraint_met_p): Handle
	AARCH64_OPND_CLASS_COND and AARCH64_OPND_COND1.
	(aarch64_print_operand): Handle AARCH64_OPND_COND1.
	* aarch64-tbl.h (aarch64_opcode_table): Use COND1 instead of
	COND for cinc, cset, cinv, csetm and cneg.
	(AARCH64_OPERANDS): Add entry for AARCH64_OPND_COND1.
	* aarch64-asm-2.c: Re-generated.
	* aarch64-dis-2.c: Ditto.
	* aarch64-opc-2.c: Ditto.

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 7078b22dfb1765fa4fc8f5663a545902c98ea1cd..371326aacf4eade03cb839e74ff8b6e7e94b994a 100644 (file)
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,7 @@
+2013-11-05  Yufeng Zhang  <yufeng.zhang@arm.com>
+
+       * config/tc-aarch64.c (parse_operands): Handle AARCH64_OPND_COND1.
+
 2013-11-05  Will Newton  <will.newton@linaro.org>
 
        PR gas/16103

diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index 02fe4de04aec5c124e8923bffdf76f98b5d5935e..4febbdcffd8ed2ec18500313a6f03f61e859a05a 100644 (file)
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -4969,6 +4969,7 @@ parse_operands (char *str, const aarch64_opcode *opcode)
          break;
 
        case AARCH64_OPND_COND:
+       case AARCH64_OPND_COND1:
          info->cond = hash_find_n (aarch64_cond_hsh, str, 2);
          str += 2;
          if (info->cond == NULL)
@@ -4976,6 +4977,13 @@ parse_operands (char *str, const aarch64_opcode *opcode)
              set_syntax_error (_("invalid condition"));
              goto failure;
            }
+         else if (operands[i] == AARCH64_OPND_COND1
+                  && (info->cond->value & 0xe) == 0xe)
+           {
+             /* Not allow AL or NV.  */
+             set_default_error ();
+             goto failure;
+           }
          break;
 
        case AARCH64_OPND_ADDR_ADRP:

diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index 8e8cdc56632342e420a40d5d2f85984eb5d84c66..8a4421626d0594eba1ea02bb437052d9082417ea 100644 (file)
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,13 @@
+2013-11-05  Yufeng Zhang  <yufeng.zhang@arm.com>
+
+       * gas/aarch64/alias.s: Add tests.
+       * gas/aarch64/alias.d: Update.
+       * gas/aarch64/no-aliases.d: Update.
+       * gas/aarch64/diagnostic.s: Add tests.
+       * gas/aarch64/diagnostic.l: Update.
+       * gas/aarch64/illegal.s: Add tests.
+       * gas/aarch64/illegal.l: Update.
+
 2013-11-05  Yufeng Zhang  <yufeng.zhang@arm.com>
 
        * gas/aarch64/diagnostic.s: Add tests of ldp/stp.

diff --git a/gas/testsuite/gas/aarch64/alias.d b/gas/testsuite/gas/aarch64/alias.d
index 53cf5e933a399594fcce284e1982bce2e95db416..5911b210201f08633f32c2907f190130f0941a07 100644 (file)
--- a/gas/testsuite/gas/aarch64/alias.d
+++ b/gas/testsuite/gas/aarch64/alias.d
@@ -96,3 +96,13 @@ Disassembly of section \.text:
  160:  2f20a448        uxtl    v8.2d, v2.2s
  164:  6f20a448        uxtl2   v8.2d, v2.4s
  168:  6f20a448        uxtl2   v8.2d, v2.4s
+ 16c:  1a81f420        csinc   w0, w1, w1, nv
+ 170:  1a81e420        csinc   w0, w1, w1, al
+ 174:  1a9ff7e0        csinc   w0, wzr, wzr, nv
+ 178:  1a9fe7e0        csinc   w0, wzr, wzr, al
+ 17c:  5a81f020        csinv   w0, w1, w1, nv
+ 180:  5a81e020        csinv   w0, w1, w1, al
+ 184:  5a9ff3e0        csinv   w0, wzr, wzr, nv
+ 188:  5a9fe3e0        csinv   w0, wzr, wzr, al
+ 18c:  5a81f420        csneg   w0, w1, w1, nv
+ 190:  5a81e420        csneg   w0, w1, w1, al

diff --git a/gas/testsuite/gas/aarch64/alias.s b/gas/testsuite/gas/aarch64/alias.s
index 0db9affbe8f8ab799468826bdfa5a7009873526d..f86b2dcd1ea898ac6c1b9b833d13c5fcc9732e1a 100644 (file)
--- a/gas/testsuite/gas/aarch64/alias.s
+++ b/gas/testsuite/gas/aarch64/alias.s
@@ -117,3 +117,14 @@
 
        asimdshll       s
        asimdshll       u
+
+       csinc   w0, w1, w1, nv
+       csinc   w0, w1, w1, al
+       csinc   w0, wzr, wzr, nv
+       csinc   w0, wzr, wzr, al
+       csinv   w0, w1, w1, nv
+       csinv   w0, w1, w1, al
+       csinv   w0, wzr, wzr, nv
+       csinv   w0, wzr, wzr, al
+       csneg   w0, w1, w1, nv
+       csneg   w0, w1, w1, al

diff --git a/gas/testsuite/gas/aarch64/diagnostic.l b/gas/testsuite/gas/aarch64/diagnostic.l
index 015e16ae3ff521419fd3ea09c62daeb7826c3d27..00a0d7a8ee1a8fb6e487324718e693cd1f8aa14f 100644 (file)
--- a/gas/testsuite/gas/aarch64/diagnostic.l
+++ b/gas/testsuite/gas/aarch64/diagnostic.l
@@ -93,3 +93,7 @@
 [^:]*:95: Error: immediate value should be a multiple of 4 at operand 3 -- `stp w0,w1,\[x2,#3\]'
 [^:]*:96: Error: immediate value should be a multiple of 4 at operand 3 -- `stp w0,w1,\[x2,#2\]!'
 [^:]*:97: Error: immediate value should be a multiple of 4 at operand 3 -- `stp w0,w1,\[x2\],#1'
+[^:]*:98: Error: operand 3 should be one of the standard conditions, excluding AL and NV. -- `cinc w0,w1,al'
+[^:]*:99: Error: operand 3 should be one of the standard conditions, excluding AL and NV. -- `cinc w0,w1,nv'
+[^:]*:100: Error: operand 2 should be one of the standard conditions, excluding AL and NV. -- `cset w0,al'
+[^:]*:101: Error: operand 2 should be one of the standard conditions, excluding AL and NV. -- `cset w0,nv'

diff --git a/gas/testsuite/gas/aarch64/diagnostic.s b/gas/testsuite/gas/aarch64/diagnostic.s
index afa04b52749dbf66d655146b702010bceb269c9d..2bb16b0087062bb00bf0f9104310f9208cb5ceb6 100644 (file)
--- a/gas/testsuite/gas/aarch64/diagnostic.s
+++ b/gas/testsuite/gas/aarch64/diagnostic.s
@@ -95,3 +95,7 @@
        stp     w0, w1, [x2, #3]
        stp     w0, w1, [x2, #2]!
        stp     w0, w1, [x2], #1
+       cinc    w0, w1, al
+       cinc    w0, w1, nv
+       cset    w0, al
+       cset    w0, nv

diff --git a/gas/testsuite/gas/aarch64/illegal.l b/gas/testsuite/gas/aarch64/illegal.l
index e36b8fefb05b8cdaf1ea1d247729f2b5f3db35f9..044b78774f02f609e9bc79bf74809f41c5e379e5 100644 (file)
--- a/gas/testsuite/gas/aarch64/illegal.l
+++ b/gas/testsuite/gas/aarch64/illegal.l
@@ -552,4 +552,14 @@
 [^:]*:544: Error: .*`fmov s0,#0xC0280000C1400000'
 [^:]*:545: Error: .*`fmov d0,#0xC02f800000000000'
 [^:]*:550: Error: .*`ands w0,w24,#0xffeefffffffffffd'
-[^:]*:553: Error: .*
+[^:]*:554: Error: .*`cinc w0,w1,al'
+[^:]*:555: Error: .*`cinc w0,w1,nv'
+[^:]*:556: Error: .*`cset w0,al'
+[^:]*:557: Error: .*`cset w0,nv'
+[^:]*:558: Error: .*`cinv w0,w1,al'
+[^:]*:559: Error: .*`cinv w0,w1,nv'
+[^:]*:560: Error: .*`csetm w0,al'
+[^:]*:561: Error: .*`csetm w0,nv'
+[^:]*:562: Error: .*`cneg w0,w1,al'
+[^:]*:563: Error: .*`cneg w0,w1,nv'
+[^:]*:563: Error: .*

diff --git a/gas/testsuite/gas/aarch64/illegal.s b/gas/testsuite/gas/aarch64/illegal.s
index a46946e8926fef347477c730c15585cd63ab4139..4578d973858fcb11a6021ef8feea5163c02e7662 100644 (file)
--- a/gas/testsuite/gas/aarch64/illegal.s
+++ b/gas/testsuite/gas/aarch64/illegal.s
@@ -550,4 +550,14 @@
        ands    w0, w24, #0xffeefffffffffffd
 
 one_label:
-       
+
+       cinc    w0, w1, al
+       cinc    w0, w1, nv
+       cset    w0, al
+       cset    w0, nv
+       cinv    w0, w1, al
+       cinv    w0, w1, nv
+       csetm   w0, al
+       csetm   w0, nv
+       cneg    w0, w1, al
+       cneg    w0, w1, nv

diff --git a/gas/testsuite/gas/aarch64/no-aliases.d b/gas/testsuite/gas/aarch64/no-aliases.d
index 1065094f28b6f06d7b11e6d07b03000ee83e23b8..fd940647cf96eeec99b290d3f25fc72ad1d555ec 100644 (file)
--- a/gas/testsuite/gas/aarch64/no-aliases.d
+++ b/gas/testsuite/gas/aarch64/no-aliases.d
@@ -97,3 +97,13 @@ Disassembly of section \.text:
  160:  2f20a448        ushll   v8.2d, v2.2s, #0
  164:  6f20a448        ushll2  v8.2d, v2.4s, #0
  168:  6f20a448        ushll2  v8.2d, v2.4s, #0
+ 16c:  1a81f420        csinc   w0, w1, w1, nv
+ 170:  1a81e420        csinc   w0, w1, w1, al
+ 174:  1a9ff7e0        csinc   w0, wzr, wzr, nv
+ 178:  1a9fe7e0        csinc   w0, wzr, wzr, al
+ 17c:  5a81f020        csinv   w0, w1, w1, nv
+ 180:  5a81e020        csinv   w0, w1, w1, al
+ 184:  5a9ff3e0        csinv   w0, wzr, wzr, nv
+ 188:  5a9fe3e0        csinv   w0, wzr, wzr, al
+ 18c:  5a81f420        csneg   w0, w1, w1, nv
+ 190:  5a81e420        csneg   w0, w1, w1, al

diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog
index f645a7e7e59b2c2df9e7e7beaf5983b9337459ce..50de99ffd04efed416536c2f491b63c54a2f2d5f 100644 (file)
--- a/include/opcode/ChangeLog
+++ b/include/opcode/ChangeLog
@@ -1,3 +1,8 @@
+2013-11-05  Yufeng Zhang  <yufeng.zhang@arm.com>
+
+       * aarch64.h (enum aarch64_operand_class): Add AARCH64_OPND_CLASS_COND.
+       (enum aarch64_opnd): Add AARCH64_OPND_COND1.
+
 2013-10-14  Chao-ying Fu  <Chao-ying.Fu@imgtec.com>
 
        * mips.h (mips_operand_type): Add OP_IMM_INDEX and OP_REG_INDEX.

diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index eaf3cda5d2f60422b50723971ac1bfa9a7180291..b45f8c042cdcf8787642bdc607866fa49379b471 100644 (file)
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -85,6 +85,7 @@ enum aarch64_operand_class
   AARCH64_OPND_CLASS_ADDRESS,
   AARCH64_OPND_CLASS_IMMEDIATE,
   AARCH64_OPND_CLASS_SYSTEM,
+  AARCH64_OPND_CLASS_COND,
 };
 
 /* Operand code that helps both parsing and coding.
@@ -168,6 +169,7 @@ enum aarch64_opnd
   AARCH64_OPND_IMM_MOV,        /* Immediate operand for the MOV alias.  */
 
   AARCH64_OPND_COND,   /* Standard condition as the last operand.  */
+  AARCH64_OPND_COND1,  /* Same as the above, but excluding AL and NV.  */
 
   AARCH64_OPND_ADDR_ADRP,      /* Memory address for ADRP */
   AARCH64_OPND_ADDR_PCREL14,   /* 14-bit PC-relative address for e.g. TBZ.  */

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 424c27f56568f5f43ad408e0159fdc9b4a0e0629..97c0459519c597e5470c139975663ac3b0b3f652 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,17 @@
+2013-11-05  Yufeng Zhang  <yufeng.zhang@arm.com>
+
+       * aarch64-dis.c (convert_ubfm_to_lsl): Check for cond != '111x'.
+       (convert_from_csel): Likewise.
+       * aarch64-opc.c (operand_general_constraint_met_p): Handle
+       AARCH64_OPND_CLASS_COND and AARCH64_OPND_COND1.
+       (aarch64_print_operand): Handle AARCH64_OPND_COND1.
+       * aarch64-tbl.h (aarch64_opcode_table): Use COND1 instead of
+       COND for cinc, cset, cinv, csetm and cneg.
+       (AARCH64_OPERANDS): Add entry for AARCH64_OPND_COND1.
+       * aarch64-asm-2.c: Re-generated.
+       * aarch64-dis-2.c: Ditto.
+       * aarch64-opc-2.c: Ditto.
+
 2013-11-05  Yufeng Zhang  <yufeng.zhang@arm.com>
 
        * aarch64-opc.c (set_syntax_error): New function.

diff --git a/opcodes/aarch64-asm-2.c b/opcodes/aarch64-asm-2.c
index 9ad9e1e3d8af989cd1fc7b29f6536de834847bd3..225ae2e7d0fdd487e7c1af40304e50fa765baee7 100644 (file)
--- a/opcodes/aarch64-asm-2.c
+++ b/opcodes/aarch64-asm-2.c
@@ -303,10 +303,10 @@ aarch64_insert_operand (const aarch64_operand *self,
     case 55:
     case 56:
     case 57:
-    case 65:
     case 66:
     case 67:
     case 68:
+    case 69:
       return aarch64_ins_imm (self, info, code, inst);
     case 37:
     case 38:
@@ -324,33 +324,34 @@ aarch64_insert_operand (const aarch64_operand *self,
     case 61:
       return aarch64_ins_fbits (self, info, code, inst);
     case 63:
+    case 64:
       return aarch64_ins_cond (self, info, code, inst);
-    case 69:
-    case 75:
-      return aarch64_ins_addr_simple (self, info, code, inst);
     case 70:
-      return aarch64_ins_addr_regoff (self, info, code, inst);
+    case 76:
+      return aarch64_ins_addr_simple (self, info, code, inst);
     case 71:
+      return aarch64_ins_addr_regoff (self, info, code, inst);
     case 72:
     case 73:
-      return aarch64_ins_addr_simm (self, info, code, inst);
     case 74:
+      return aarch64_ins_addr_simm (self, info, code, inst);
+    case 75:
       return aarch64_ins_addr_uimm12 (self, info, code, inst);
-    case 76:
-      return aarch64_ins_simd_addr_post (self, info, code, inst);
     case 77:
-      return aarch64_ins_sysreg (self, info, code, inst);
+      return aarch64_ins_simd_addr_post (self, info, code, inst);
     case 78:
-      return aarch64_ins_pstatefield (self, info, code, inst);
+      return aarch64_ins_sysreg (self, info, code, inst);
     case 79:
+      return aarch64_ins_pstatefield (self, info, code, inst);
     case 80:
     case 81:
     case 82:
-      return aarch64_ins_sysins_op (self, info, code, inst);
     case 83:
+      return aarch64_ins_sysins_op (self, info, code, inst);
     case 84:
-      return aarch64_ins_barrier (self, info, code, inst);
     case 85:
+      return aarch64_ins_barrier (self, info, code, inst);
+    case 86:
       return aarch64_ins_prfop (self, info, code, inst);
     default: assert (0); abort ();
     }

diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c
index 0d633eb5a4eeddd0ccf49b423b48c4cb4a15977b..32e2fc0f04fe477b53cc2e530b5235818b1e8771 100644 (file)
--- a/opcodes/aarch64-dis-2.c
+++ b/opcodes/aarch64-dis-2.c
@@ -7690,11 +7690,11 @@ aarch64_extract_operand (const aarch64_operand *self,
     case 55:
     case 56:
     case 57:
-    case 64:
     case 65:
     case 66:
     case 67:
     case 68:
+    case 69:
       return aarch64_ext_imm (self, info, code, inst);
     case 37:
     case 38:
@@ -7714,33 +7714,34 @@ aarch64_extract_operand (const aarch64_operand *self,
     case 61:
       return aarch64_ext_fbits (self, info, code, inst);
     case 63:
+    case 64:
       return aarch64_ext_cond (self, info, code, inst);
-    case 69:
-    case 75:
-      return aarch64_ext_addr_simple (self, info, code, inst);
     case 70:
-      return aarch64_ext_addr_regoff (self, info, code, inst);
+    case 76:
+      return aarch64_ext_addr_simple (self, info, code, inst);
     case 71:
+      return aarch64_ext_addr_regoff (self, info, code, inst);
     case 72:
     case 73:
-      return aarch64_ext_addr_simm (self, info, code, inst);
     case 74:
+      return aarch64_ext_addr_simm (self, info, code, inst);
+    case 75:
       return aarch64_ext_addr_uimm12 (self, info, code, inst);
-    case 76:
-      return aarch64_ext_simd_addr_post (self, info, code, inst);
     case 77:
-      return aarch64_ext_sysreg (self, info, code, inst);
+      return aarch64_ext_simd_addr_post (self, info, code, inst);
     case 78:
-      return aarch64_ext_pstatefield (self, info, code, inst);
+      return aarch64_ext_sysreg (self, info, code, inst);
     case 79:
+      return aarch64_ext_pstatefield (self, info, code, inst);
     case 80:
     case 81:
     case 82:
-      return aarch64_ext_sysins_op (self, info, code, inst);
     case 83:
+      return aarch64_ext_sysins_op (self, info, code, inst);
     case 84:
-      return aarch64_ext_barrier (self, info, code, inst);
     case 85:
+      return aarch64_ext_barrier (self, info, code, inst);
+    case 86:
       return aarch64_ext_prfop (self, info, code, inst);
     default: assert (0); abort ();
     }

diff --git a/opcodes/aarch64-dis.c b/opcodes/aarch64-dis.c
index c403be85ca90b9578cda50492299839f67399ea0..c11f78f78ab8569db6ebf5295d8047aeeee338bd 100644 (file)
--- a/opcodes/aarch64-dis.c
+++ b/opcodes/aarch64-dis.c
@@ -1601,12 +1601,14 @@ convert_ubfm_to_lsl (aarch64_inst *inst)
 
 /* CINC <Wd>, <Wn>, <cond>
      is equivalent to:
-   CSINC <Wd>, <Wn>, <Wn>, invert(<cond>).  */
+   CSINC <Wd>, <Wn>, <Wn>, invert(<cond>)
+     where <cond> is not AL or NV.  */
 
 static int
 convert_from_csel (aarch64_inst *inst)
 {
-  if (inst->operands[1].reg.regno == inst->operands[2].reg.regno)
+  if (inst->operands[1].reg.regno == inst->operands[2].reg.regno
+      && (inst->operands[3].cond->value & 0xe) != 0xe)
     {
       copy_operand_info (inst, 2, 3);
       inst->operands[2].cond = get_inverted_cond (inst->operands[3].cond);
@@ -1618,13 +1620,15 @@ convert_from_csel (aarch64_inst *inst)
 
 /* CSET <Wd>, <cond>
      is equivalent to:
-   CSINC <Wd>, WZR, WZR, invert(<cond>).  */
+   CSINC <Wd>, WZR, WZR, invert(<cond>)
+     where <cond> is not AL or NV.  */
 
 static int
 convert_csinc_to_cset (aarch64_inst *inst)
 {
   if (inst->operands[1].reg.regno == 0x1f
-      && inst->operands[2].reg.regno == 0x1f)
+      && inst->operands[2].reg.regno == 0x1f
+      && (inst->operands[3].cond->value & 0xe) != 0xe)
     {
       copy_operand_info (inst, 1, 3);
       inst->operands[1].cond = get_inverted_cond (inst->operands[3].cond);

diff --git a/opcodes/aarch64-opc-2.c b/opcodes/aarch64-opc-2.c
index 08010eb4541db01c633f3613bcb0113c8d7cdda0..7c4d6af2c22b7813546df2004ee418b761fa1309 100644 (file)
--- a/opcodes/aarch64-opc-2.c
+++ b/opcodes/aarch64-opc-2.c
@@ -87,7 +87,8 @@ const struct aarch64_operand aarch64_operands[] =
   {AARCH64_OPND_CLASS_IMMEDIATE, "HALF", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm16}, "a 16-bit immediate with optional left shift"},
   {AARCH64_OPND_CLASS_IMMEDIATE, "FBITS", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_scale}, "the number of bits after the binary point in the fixed-point value"},
   {AARCH64_OPND_CLASS_IMMEDIATE, "IMM_MOV", 0, {}, "an immediate"},
-  {AARCH64_OPND_CLASS_NIL, "COND", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a condition"},
+  {AARCH64_OPND_CLASS_COND, "COND", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a condition"},
+  {AARCH64_OPND_CLASS_COND, "COND1", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "one of the standard conditions, excluding AL and NV."},
   {AARCH64_OPND_CLASS_ADDRESS, "ADDR_ADRP", OPD_F_SEXT | OPD_F_HAS_EXTRACTOR, {FLD_immhi, FLD_immlo}, "21-bit PC-relative address of a 4KB page"},
   {AARCH64_OPND_CLASS_ADDRESS, "ADDR_PCREL14", OPD_F_SEXT | OPD_F_SHIFT_BY_2 | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm14}, "14-bit PC-relative address"},
   {AARCH64_OPND_CLASS_ADDRESS, "ADDR_PCREL19", OPD_F_SEXT | OPD_F_SHIFT_BY_2 | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm19}, "19-bit PC-relative address"},

diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index 0d16bd64767c5acfccae5221c679118839a5e39d..4a6895cb690f46f671fbe65bdd37a630692c11fd 100644 (file)
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -1286,6 +1286,15 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
        }
       break;
 
+    case AARCH64_OPND_CLASS_COND:
+      if (type == AARCH64_OPND_COND1
+         && (opnds[idx].cond->value & 0xe) == 0xe)
+       {
+         /* Not allow AL or NV.  */
+         set_syntax_error (mismatch_detail, idx, NULL);
+       }
+      break;
+
     case AARCH64_OPND_CLASS_ADDRESS:
       /* Check writeback.  */
       switch (opcode->iclass)
@@ -2524,6 +2533,7 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
       break;
 
     case AARCH64_OPND_COND:
+    case AARCH64_OPND_COND1:
       snprintf (buf, size, "%s", opnd->cond->names[0]);
       break;
 

diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 7c77768329e774c55ecc89ecf1d85d2c7e336688..c53794a0d068feaad1df395b8fd1cb883f75a64b 100644 (file)
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -1782,13 +1782,13 @@ struct aarch64_opcode aarch64_opcode_table[] =
   /* Conditional select.  */
   {"csel", 0x1a800000, 0x7fe00c00, condsel, 0, CORE, OP4 (Rd, Rn, Rm, COND), QL_CSEL, F_SF},
   {"csinc", 0x1a800400, 0x7fe00c00, condsel, 0, CORE, OP4 (Rd, Rn, Rm, COND), QL_CSEL, F_HAS_ALIAS | F_SF},
-  {"cinc", 0x1a800400, 0x7fe00c00, condsel, OP_CINC, CORE, OP3 (Rd, Rn, COND), QL_CSEL, F_ALIAS | F_SF | F_CONV},
-  {"cset", 0x1a9f07e0, 0x7fff0fe0, condsel, OP_CSET, CORE, OP2 (Rd, COND), QL_DST_R, F_ALIAS | F_P1 | F_SF | F_CONV},
+  {"cinc", 0x1a800400, 0x7fe00c00, condsel, OP_CINC, CORE, OP3 (Rd, Rn, COND1), QL_CSEL, F_ALIAS | F_SF | F_CONV},
+  {"cset", 0x1a9f07e0, 0x7fff0fe0, condsel, OP_CSET, CORE, OP2 (Rd, COND1), QL_DST_R, F_ALIAS | F_P1 | F_SF | F_CONV},
   {"csinv", 0x5a800000, 0x7fe00c00, condsel, 0, CORE, OP4 (Rd, Rn, Rm, COND), QL_CSEL, F_HAS_ALIAS | F_SF},
-  {"cinv", 0x5a800000, 0x7fe00c00, condsel, OP_CINV, CORE, OP3 (Rd, Rn, COND), QL_CSEL, F_ALIAS | F_SF | F_CONV},
-  {"csetm", 0x5a9f03e0, 0x7fff0fe0, condsel, OP_CSETM, CORE, OP2 (Rd, COND), QL_DST_R, F_ALIAS | F_P1 | F_SF | F_CONV},
+  {"cinv", 0x5a800000, 0x7fe00c00, condsel, OP_CINV, CORE, OP3 (Rd, Rn, COND1), QL_CSEL, F_ALIAS | F_SF | F_CONV},
+  {"csetm", 0x5a9f03e0, 0x7fff0fe0, condsel, OP_CSETM, CORE, OP2 (Rd, COND1), QL_DST_R, F_ALIAS | F_P1 | F_SF | F_CONV},
   {"csneg", 0x5a800400, 0x7fe00c00, condsel, 0, CORE, OP4 (Rd, Rn, Rm, COND), QL_CSEL, F_HAS_ALIAS | F_SF},
-  {"cneg", 0x5a800400, 0x7fe00c00, condsel, OP_CNEG, CORE, OP3 (Rd, Rn, COND), QL_CSEL, F_ALIAS | F_SF | F_CONV},
+  {"cneg", 0x5a800400, 0x7fe00c00, condsel, OP_CNEG, CORE, OP3 (Rd, Rn, COND1), QL_CSEL, F_ALIAS | F_SF | F_CONV},
   /* Crypto AES.  */
   {"aese", 0x4e284800, 0xfffffc00, cryptoaes, 0, CRYPTO, OP2 (Vd, Vn), QL_V2SAME16B, 0},
   {"aesd", 0x4e285800, 0xfffffc00, cryptoaes, 0, CRYPTO, OP2 (Vd, Vn), QL_V2SAME16B, 0},
@@ -2235,7 +2235,9 @@ struct aarch64_opcode aarch64_opcode_table[] =
     Y(IMMEDIATE, fbits, "FBITS", 0, F(FLD_scale),                      \
       "the number of bits after the binary point in the fixed-point value")\
     X(IMMEDIATE, 0, 0, "IMM_MOV", 0, F(), "an immediate")              \
-    Y(NIL, cond, "COND", 0, F(), "a condition")                                \
+    Y(COND, cond, "COND", 0, F(), "a condition")                       \
+    Y(COND, cond, "COND1", 0, F(),                                     \
+      "one of the standard conditions, excluding AL and NV.")          \
     X(ADDRESS, 0, ext_imm, "ADDR_ADRP", OPD_F_SEXT, F(FLD_immhi, FLD_immlo),\
       "21-bit PC-relative address of a 4KB page")                      \
     Y(ADDRESS, imm, "ADDR_PCREL14", OPD_F_SEXT | OPD_F_SHIFT_BY_2,     \