make
## Building microwatt-verilator using the libre-soc core
+
cd /path/to/soc
make microwatt_external_core
cp external_core_top.v /path/to/microwatt
make microwatt-verilator
## Running the simulation
+
cp microwatt/arch/powerpc/boot/dtbImage.microwatt
./microwatt-verilator sdram_init.bin dtbImage.microwatt
+
+## Building the bitstring for OrangeCrab
+
+ cd microwatt
+ export FPGA_TARGET=ORANGE-CRAB
+ export GHDLSYNTH=ghdl
+ make microwatt.bit
+
+
## TODO: buildroot