&& REGNO (reg1) < FIRST_PSEUDO_REGISTER
&& REGNO (reg2) >= FIRST_PSEUDO_REGISTER
&& GET_MODE (reg1) == Pmode
- && !have_addptr3_insn (gen_reg_rtx (Pmode), reg1,
+ && !have_addptr3_insn (lra_pmode_pseudo, reg1,
XEXP (XEXP (SET_SRC (set), 0), 1)))
{
XEXP (XEXP (SET_SRC (set), 0), 0) = op2;
extern int lra_new_regno_start;
extern int lra_constraint_new_regno_start;
extern int lra_bad_spill_regno_start;
+extern rtx lra_pmode_pseudo;
extern bitmap_head lra_inheritance_pseudos;
extern bitmap_head lra_split_regs;
extern bitmap_head lra_subreg_reload_pseudos;
it is possible. */
int lra_bad_spill_regno_start;
+/* A pseudo of Pmode. */
+rtx lra_pmode_pseudo;
+
/* Inheritance pseudo regnos before the new spill pass. */
bitmap_head lra_inheritance_pseudos;
lra_dump_file = f;
lra_asm_error_p = false;
+ lra_pmode_pseudo = gen_reg_rtx (Pmode);
timevar_push (TV_LRA);
--- /dev/null
+/* { dg-do compile } */
+/* { dg-options "-fstrict-aliasing -O" } */
+
+typedef struct {
+ _Complex e;
+ _Complex f;
+ _Complex g;
+ _Complex h;
+ _Complex i;
+ _Complex j;
+ _Complex k;
+ _Complex l;
+ _Complex m;
+ _Complex n;
+ _Complex o;
+ _Complex p;
+} Scl16;
+
+Scl16 g1sScl16, g2sScl16, g3sScl16, g4sScl16, g5sScl16, g6sScl16, g7sScl16,
+ g8sScl16, g9sScl16, g10sScl16, g11sScl16, g12sScl16, g13sScl16, g14sScl16,
+ g15sScl16, g16sScl16;
+
+void testvaScl16();
+
+void
+testitScl16() {
+ testvaScl16(g10sScl16, g11sScl16, g12sScl16, g13sScl16, g14sScl16, g1sScl16,
+ g2sScl16, g3sScl16, g4sScl16, g5sScl16, g6sScl16, g7sScl16,
+ g8sScl16, g9sScl16, g10sScl16, g11sScl16, g12sScl16, g13sScl16,
+ g14sScl16, g15sScl16, g16sScl16);
+}