add riscv-sifive-elf triple

diff --git a/litex/soc/cores/cpu/blackparrot/core.py b/litex/soc/cores/cpu/blackparrot/core.py
index dfb790c005ebb34e882a092e896892f65dee2d8d..b58ac1a1d2fa42fc7c551cadf738b28b7825a701 100644 (file)
--- a/litex/soc/cores/cpu/blackparrot/core.py
+++ b/litex/soc/cores/cpu/blackparrot/core.py
@@ -48,7 +48,7 @@ class BlackParrotRV64(CPU):
     name                 = "blackparrot"
     data_width           = 64
     endianness           = "little"
-    gcc_triple           = ("riscv64-unknown-elf", "riscv64-linux")
+    gcc_triple           = ("riscv64-unknown-elf", "riscv64-linux", "riscv-sifive-elf")
     linker_output_format = "elf64-littleriscv"
     io_regions           = {0x30000000: 0x20000000} # origin, length
 

diff --git a/litex/soc/cores/cpu/minerva/core.py b/litex/soc/cores/cpu/minerva/core.py
index 9bc970895949faba23d2728507485f730ba9a3ff..2c3d967cb8d7e21cec32623fb5d935e1d7f6cddb 100644 (file)
--- a/litex/soc/cores/cpu/minerva/core.py
+++ b/litex/soc/cores/cpu/minerva/core.py
@@ -18,7 +18,7 @@ class Minerva(CPU):
     data_width           = 32
     endianness           = "little"
     gcc_triple           = ("riscv64-unknown-elf", "riscv32-unknown-elf", "riscv-none-embed",
-                            "riscv64-linux")
+                            "riscv64-linux", "riscv-sifive-elf")
     linker_output_format = "elf32-littleriscv"
     io_regions           = {0x80000000: 0x80000000} # origin, length
 

diff --git a/litex/soc/cores/cpu/picorv32/core.py b/litex/soc/cores/cpu/picorv32/core.py
index c2122677c971ca3585f8c8e1b747a415b025b402..0729af1c06306236fff2cce9c192568501f65a7a 100644 (file)
--- a/litex/soc/cores/cpu/picorv32/core.py
+++ b/litex/soc/cores/cpu/picorv32/core.py
@@ -35,7 +35,7 @@ class PicoRV32(CPU):
     data_width           = 32
     endianness           = "little"
     gcc_triple           = ("riscv64-unknown-elf", "riscv32-unknown-elf", "riscv-none-embed",
-                            "riscv64-linux")
+                            "riscv64-linux", "riscv-sifive-elf")
     linker_output_format = "elf32-littleriscv"
     io_regions           = {0x80000000: 0x80000000} # origin, length
 

diff --git a/litex/soc/cores/cpu/rocket/core.py b/litex/soc/cores/cpu/rocket/core.py
index 108a49678d8428bf22d8ed6cf68bb9bac2bbff0c..3f94cf2dfcf4098638842db200a299524a1b1e31 100644 (file)
--- a/litex/soc/cores/cpu/rocket/core.py
+++ b/litex/soc/cores/cpu/rocket/core.py
@@ -67,7 +67,7 @@ class RocketRV64(CPU):
     name                 = "rocket"
     data_width           = 64
     endianness           = "little"
-    gcc_triple           = ("riscv64-unknown-elf", "riscv64-linux")
+    gcc_triple           = ("riscv64-unknown-elf", "riscv64-linux", "riscv-sifive-elf")
     linker_output_format = "elf64-littleriscv"
     io_regions           = {0x10000000: 0x70000000} # origin, length
 

diff --git a/litex/soc/cores/cpu/vexriscv/core.py b/litex/soc/cores/cpu/vexriscv/core.py
index 08c2c8a26c4ec37ab5c896d89b883de8ea807b36..996cbf76d75749432de84e3a3258a67000831a39 100644 (file)
--- a/litex/soc/cores/cpu/vexriscv/core.py
+++ b/litex/soc/cores/cpu/vexriscv/core.py
@@ -79,7 +79,7 @@ class VexRiscv(CPU, AutoCSR):
     data_width           = 32
     endianness           = "little"
     gcc_triple           = ("riscv64-unknown-elf", "riscv32-unknown-elf", "riscv-none-embed",
-                            "riscv64-linux")
+                            "riscv64-linux", "riscv-sifive-elf")
     linker_output_format = "elf32-littleriscv"
     io_regions           = {0x80000000: 0x80000000} # origin, length