Clean up pseudo-private member usage in `backends/spice/spice.cc`.

diff --git a/backends/spice/spice.cc b/backends/spice/spice.cc
index 6738a4bbd6c4a9e7bd10b5847f0bb337283079a9..9b603a8c57befd2903bfff4a4f688abbbb046c52 100644 (file)
--- a/backends/spice/spice.cc
+++ b/backends/spice/spice.cc
@@ -70,14 +70,13 @@ static void print_spice_module(std::ostream &f, RTLIL::Module *module, RTLIL::De
        idict<IdString, 1> inums;
        int cell_counter = 0, conn_counter = 0, nc_counter = 0;
 
-       for (auto &cell_it : module->cells_)
+       for (auto cell : module->cells())
        {
-               RTLIL::Cell *cell = cell_it.second;
                f << stringf("X%d", cell_counter++);
 
                std::vector<RTLIL::SigSpec> port_sigs;
 
-               if (design->modules_.count(cell->type) == 0)
+               if (design->module(cell->type) == nullptr)
                {
                        log_warning("no (blackbox) module for cell type `%s' (%s.%s) found! Guessing order of ports.\n",
                                        log_id(cell->type), log_id(module), log_id(cell));
@@ -88,11 +87,10 @@ static void print_spice_module(std::ostream &f, RTLIL::Module *module, RTLIL::De
                }
                else
                {
-                       RTLIL::Module *mod = design->modules_.at(cell->type);
+                       RTLIL::Module *mod = design->module(cell->type);
 
                        std::vector<RTLIL::Wire*> ports;
-                       for (auto wire_it : mod->wires_) {
-                               RTLIL::Wire *wire = wire_it.second;
+                       for (auto wire : mod->wires()) {
                                if (wire->port_id == 0)
                                        continue;
                                while (int(ports.size()) < wire->port_id)
@@ -202,16 +200,15 @@ struct SpiceBackend : public Backend {
                extra_args(f, filename, args, argidx);
 
                if (top_module_name.empty())
-                       for (auto & mod_it:design->modules_)
-                               if (mod_it.second->get_bool_attribute("\\top"))
-                                       top_module_name = mod_it.first.str();
+                       for (auto module : design->modules())
+                               if (module->get_bool_attribute("\\top"))
+                                       top_module_name = module->name.str();
 
                *f << stringf("* SPICE netlist generated by %s\n", yosys_version_str);
                *f << stringf("\n");
 
-               for (auto module_it : design->modules_)
+               for (auto module : design->modules())
                {
-                       RTLIL::Module *module = module_it.second;
                        if (module->get_blackbox_attribute())
                                continue;
 
@@ -226,8 +223,7 @@ struct SpiceBackend : public Backend {
                        }
 
                        std::vector<RTLIL::Wire*> ports;
-                       for (auto wire_it : module->wires_) {
-                               RTLIL::Wire *wire = wire_it.second;
+                       for (auto wire : module->wires()) {
                                if (wire->port_id == 0)
                                        continue;
                                while (int(ports.size()) < wire->port_id)