add Trigger

diff --git a/migScope/__init__.py b/migScope/__init__.py
index 0bb5075702a0e7629d6c701733ec273724f8aa51..d8ee29bad5d896092ae222a04b850e4922345b67 100644 (file)
--- a/migScope/__init__.py
+++ b/migScope/__init__.py
@@ -145,10 +145,9 @@ class Sum:
                self.pipe = pipe
                self.prog_mode = prog_mode
                assert (size <= 4), "size > 4 (This version support only non cascadable SRL16)"
-               self.i0 = Signal()
-               self.i1 = Signal()
-               self.i2 = Signal()
-               self.i3 = Signal()
+               self.i = Array(Signal() for j in range(4))
+               for j in range(4):
+                       self.i[j].name_override = "i%d"%j
                
                self._ce = Signal()
                self._shift_in = Signal()
@@ -197,10 +196,10 @@ class Sum:
                inst = [
                        Instance("SRLC16E",
                                [
-                               ("a0", self.i0),
-                               ("a1", self.i1),
-                               ("a2", self.i2),
-                               ("a3", self.i3),
+                               ("a0", self.i[0]),
+                               ("a1", self.i[1]),
+                               ("a2", self.i[2]),
+                               ("a3", self.i[3]),
                                ("ce", self._ce),
                                ("d", self._shift_in)
                                ] , [
@@ -219,6 +218,45 @@ class Sum:
                else:
                        comb += [self.o.eq(self._o)]
                return Fragment(comb=comb,sync=sync,instances=inst)
+               
+
+class Trigger:
+       def __init__(self,address, trig_width, dat_width, ports):
+               self.trig_width = trig_width
+               self.dat_width = dat_width
+               self.ports = ports
+               assert (len(self.ports) <= 4), "Nb Ports > 4 (This version support 4 ports Max)"
+               
+               self.in_trig = Signal(BV(self.trig_width))
+               self.in_dat  = Signal(BV(self.dat_width))
+               
+               self.hit = Signal()
+               self.dat = Signal(BV(self.dat_width))
+               
+               
+       def get_fragment(self):
+               comb = []
+               sync = []
+               # Connect in_trig to input of trig elements
+               comb+= [port.i.eq(self.in_trig) for port in self.ports]
+               
+               # Connect output of trig elements to sum
+               # Todo : Add sum tree to have more that 4 inputs
+               _sum = Sum(len(self.ports))
+               comb+= [_sum.i[j].eq(self.ports[j].o) for j in range(len(self.ports))]
+               
+               # Connect sum ouput to hit
+               comb+= [self.hit.eq(_sum.o)]
+               
+               # Add ports & sum to frag
+               frag = _sum.get_fragment()
+               for port in self.ports:
+                       frag += port.get_fragment()
+
+               
+               comb+= [self.dat.eq(self.in_dat)]
+               
+               return frag + _sum.get_fragment() + Fragment(comb=comb, sync=sync)
 
 
 class Storage:
@@ -388,6 +426,9 @@ class Recorder:
                return self.bank.get_fragment()+\
                        self.storage.get_fragment()+self.sequencer.get_fragment()+\
                        Fragment(comb=comb, sync=sync)
+                       
+
+
 
 class MigCon:
        pass

diff --git a/top.py b/top.py
index 5949d32c07b535fd19813c7d3d0c6ecc532b2eb7..e2b3eb971206ad96d1d00b3b51eeb92d6074d972 100644 (file)
--- a/top.py
+++ b/top.py
@@ -66,6 +66,16 @@ import migScope
 #
 #Test Recorder
 #
-recorder = migScope.Recorder(0,32,1024)
-v = verilog.convert(recorder.get_fragment())
+#recorder = migScope.Recorder(0,32,1024)
+#v = verilog.convert(recorder.get_fragment())
+#print(v)
+
+
+term0 = migScope.Term(32)
+term1 = migScope.Term(32)
+term2 = migScope.Term(32)
+term3 = migScope.Term(32)
+
+trigger0 = migScope.Trigger(0,32,64,[term0, term1, term2, term3])
+v = verilog.convert(trigger0.get_fragment())
 print(v)