(no commit message)

diff --git a/openpower/sv/compliancy_levels.mdwn b/openpower/sv/compliancy_levels.mdwn
index 8549265529d73501915b495a6e821fe4cc59557e..6299b3eb526f17ac2fe6d56ce5cbfc6744f8e9cf 100644 (file)
--- a/openpower/sv/compliancy_levels.mdwn
+++ b/openpower/sv/compliancy_levels.mdwn
@@ -44,7 +44,11 @@ permitted to declare meeting the 3D/Advanced Level unless implementing
 
 # Ultra-Embedded Level
 
-This level is the bare minimum requirements, where everything with the
+This level exists as an entry-level into SVP64, most suited to resource
+constrained soft cores, or Hardware implementations where cost is a
+higher priority than execution speed.
+
+This level sets the bare minimum requirements, where everything with the
 exception of the `setvl` instruction may be software-emulated through
 JIT Translation or Illegal Instruction traps.  SVSTATE joins MSR and PC
 as direct peers and must be switched on any context-switch (Trap or
@@ -55,5 +59,16 @@ Exception)
 * SVSTATE **must** also be saved/restored to/from SVSRR1
 
 Any implementation that implements Hypervisor Mode must also
-correspondingly follow the Power ISA Spec for HSRR0 and HSRR1,
-and must save/restore SVSTATE to/from HSVSRR1.
+correspondingly follow the Power ISA Spec guidelines for HSRR0 and HSRR1,
+and must save/restore SVSTATE to/from HSVSRR1 in all circumstances
+involving save/restore to/from HSRR0 and HSRR1.
+
+Illegal Instruction Trap **must** be raised on:
+
+* Any SV instructions not implemented
+* any unimplemented SV Context SPRs read or written 
+* all unimplemented uses of the SVP64 Prefix
+
+Implementors are free and clear to implement any other features of
+SVP64 however only by meeting all of the mandatory requirements above
+will Compliance with the Ultra-Embedded Level be achieved.