this change was necessary since the impl csr is gone.
#define MAXVL (h->get_ct_state()->maxvl)
#define VL (h->get_ct_state()->vl)
#define UTIDX (h->get_ct_state()->count)
+#define PREC (h->get_ct_state()->prec)
#define VF_PC (h->get_ct_state()->vf_pc)
#define WRITE_NXPR(nxprnext) (h->get_ct_state()->nxpr = (nxprnext))
#define WRITE_NFPR(nfprnext) (h->get_ct_state()->nfpr = (nfprnext))
#define MASK_VXCPTAUX 0xfffff07f
#define MASK_VXCPTCAUSE 0xfffff07f
#define MASK_VXCPTEVAC 0xfff07fff
-#define MASK_VXCPTHOLD 0xffffffff
+#define MASK_VXCPTHOLD 0xfff07fff
#define MASK_VXCPTKILL 0xffffffff
#define MASK_VXCPTRESTORE 0xfff07fff
#define MASK_VXCPTSAVE 0xfff07fff
DISASM_INSN("vxcptcause", vxcptcause, 0, {&xrd});
DISASM_INSN("vxcptaux", vxcptaux, 0, {&xrd});
- DISASM_INSN("vxcptsave", vxcptsave, 0, {&xrs1});
- DISASM_INSN("vxcptrestore", vxcptrestore, 0, {&xrs1});
+ DISASM_INSN("vxcptevac", vxcptevac, 0, {&xrs1});
+ DISASM_INSN("vxcpthold", vxcpthold, 0, {&xrs1});
DISASM_INSN("vxcptkill", vxcptkill, 0, {});
const uint32_t mask_vseglen = 0x7UL << 29;
--- /dev/null
+require_supervisor_hwacha;
+reg_t addr = XS1;
+
+#define STORE_B(addr, value) \
+ p->get_mmu()->store_uint8(addr, value); \
+ addr += 1; \
+
+#define STORE_W(addr, value) \
+ p->get_mmu()->store_uint32(addr, value); \
+ addr += 4; \
+
+#define STORE_D(addr, value) \
+ p->get_mmu()->store_uint64(addr, value); \
+ addr += 8; \
+
+// to be compliant with the evac structure
+STORE_D(addr, (uint64_t)-1);
+
+STORE_W(addr, NXPR);
+STORE_W(addr, NFPR);
+STORE_W(addr, MAXVL);
+STORE_W(addr, VL);
+STORE_W(addr, UTIDX);
+STORE_W(addr, PREC);
+
+STORE_D(addr, VF_PC);
+
+for (uint32_t x=1; x<NXPR; x++) {
+ for (uint32_t i=0; i<VL; i++) {
+ STORE_D(addr, UT_READ_XPR(i, x));
+ }
+}
+
+for (uint32_t f=0; f<NFPR; f++) {
+ for (uint32_t i=0; i<VL; i++) {
+ STORE_D(addr, UT_READ_FPR(i, f));
+ }
+}
+
+for (uint32_t i=0; i<VL; i++) {
+ STORE_B(addr, h->get_ut_state(i)->run);
+}
+
+#undef STORE_B
+#undef STORE_W
+#undef STORE_D
+
+#include "insns/vxcptkill.h"
--- /dev/null
+require_supervisor_hwacha;
+reg_t addr = XS1;
+
+#define LOAD_B(addr) \
+ (addr += 1, p->get_mmu()->load_uint8(addr-1))
+
+#define LOAD_W(addr) \
+ (addr += 4, p->get_mmu()->load_uint32(addr-4))
+
+#define LOAD_D(addr) \
+ (addr += 8, p->get_mmu()->load_uint64(addr-8))
+
+// to be compliant with the evac structure
+addr += 8;
+
+WRITE_NXPR(LOAD_W(addr));
+WRITE_NFPR(LOAD_W(addr));
+WRITE_MAXVL(LOAD_W(addr));
+WRITE_VL(LOAD_W(addr));
+WRITE_UTIDX(LOAD_W(addr));
+WRITE_PREC(LOAD_W(addr));
+WRITE_VF_PC(LOAD_D(addr));
+
+for (uint32_t x=1; x<NXPR; x++) {
+ for (uint32_t i=0; i<VL; i++) {
+ UT_WRITE_XPR(i, x, LOAD_D(addr));
+ }
+}
+
+for (uint32_t f=0; f<NFPR; f++) {
+ for (uint32_t i=0; i<VL; i++) {
+ UT_WRITE_FPR(i, f, LOAD_D(addr));
+ }
+}
+
+for (uint32_t i=0; i<VL; i++) {
+ h->get_ut_state(i)->run = LOAD_B(addr);
+}
+
+#undef LOAD_B
+#undef LOAD_W
+#undef LOAD_D
+++ /dev/null
-require_supervisor_hwacha;
-reg_t addr = XS1;
-
-#define LOAD_B(addr) \
- (addr += 1, p->get_mmu()->load_uint8(addr-1))
-
-#define LOAD_W(addr) \
- (addr += 4, p->get_mmu()->load_uint32(addr-4))
-
-#define LOAD_D(addr) \
- (addr += 8, p->get_mmu()->load_uint64(addr-8))
-
-
-WRITE_NXPR(LOAD_W(addr));
-WRITE_NFPR(LOAD_W(addr));
-WRITE_MAXVL(LOAD_W(addr));
-WRITE_VL(LOAD_W(addr));
-WRITE_UTIDX(LOAD_W(addr));
-addr += 4;
-WRITE_VF_PC(LOAD_D(addr));
-
-for (uint32_t x=1; x<NXPR; x++) {
- for (uint32_t i=0; i<VL; i++) {
- UT_WRITE_XPR(i, x, LOAD_D(addr));
- }
-}
-
-for (uint32_t f=0; f<NFPR; f++) {
- for (uint32_t i=0; i<VL; i++) {
- UT_WRITE_FPR(i, f, LOAD_D(addr));
- }
-}
-
-for (uint32_t i=0; i<VL; i++) {
- h->get_ut_state(i)->run = LOAD_B(addr);
-}
-
-#undef LOAD_B
-#undef LOAD_W
-#undef LOAD_D
+++ /dev/null
-require_supervisor_hwacha;
-reg_t addr = XS1;
-
-#define STORE_B(addr, value) \
- p->get_mmu()->store_uint8(addr, value); \
- addr += 1; \
-
-#define STORE_W(addr, value) \
- p->get_mmu()->store_uint32(addr, value); \
- addr += 4; \
-
-#define STORE_D(addr, value) \
- p->get_mmu()->store_uint64(addr, value); \
- addr += 8; \
-
-STORE_W(addr, NXPR);
-STORE_W(addr, NFPR);
-STORE_W(addr, MAXVL);
-STORE_W(addr, VL);
-STORE_W(addr, UTIDX);
-addr += 4;
-STORE_D(addr, VF_PC);
-
-for (uint32_t x=1; x<NXPR; x++) {
- for (uint32_t i=0; i<VL; i++) {
- STORE_D(addr, UT_READ_XPR(i, x));
- }
-}
-
-for (uint32_t f=0; f<NFPR; f++) {
- for (uint32_t i=0; i<VL; i++) {
- STORE_D(addr, UT_READ_FPR(i, f));
- }
-}
-
-for (uint32_t i=0; i<VL; i++) {
- STORE_B(addr, h->get_ut_state(i)->run);
-}
-
-#undef STORE_B
-#undef STORE_W
-#undef STORE_D
-
-#include "insns/vxcptkill.h"
DECLARE_INSN(vssegw, MATCH_VSSEGW, MASK_VSSEGW)
DECLARE_INSN(vxcptaux, MATCH_VXCPTAUX, MASK_VXCPTAUX)
DECLARE_INSN(vxcptcause, MATCH_VXCPTCAUSE, MASK_VXCPTCAUSE)
+DECLARE_INSN(vxcptevac, MATCH_VXCPTEVAC, MASK_VXCPTEVAC)
+DECLARE_INSN(vxcpthold, MATCH_VXCPTHOLD, MASK_VXCPTHOLD)
DECLARE_INSN(vxcptkill, MATCH_VXCPTKILL, MASK_VXCPTKILL)
-DECLARE_INSN(vxcptrestore, MATCH_VXCPTRESTORE, MASK_VXCPTRESTORE)
-DECLARE_INSN(vxcptsave, MATCH_VXCPTSAVE, MASK_VXCPTSAVE)