* ppc.h (PPC_OPCODE_440): Define. Formatting. Use hex for other

	PPC_OPCODE_* defines.

diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog
index 5c40b419e3029d90658e10381ea14b15e808e5e6..8aa84533eaf73a0afe12d99e8a24c4fcc18f23d4 100644 (file)
--- a/include/opcode/ChangeLog
+++ b/include/opcode/ChangeLog
@@ -1,3 +1,8 @@
+2003-08-19  Alan Modra  <amodra@bigpond.net.au>
+
+       * ppc.h (PPC_OPCODE_440): Define.  Formatting.  Use hex for other
+       PPC_OPCODE_* defines.
+
 2003-08-16  Jason Eckhardt  <jle@rice.edu>
 
        * i860.h (fmov.ds): Expand as famov.ds.

diff --git a/include/opcode/ppc.h b/include/opcode/ppc.h
index 80b39cdaefb76a99bcac793c77332b7b47d34d32..342237e8dd6956f44e66260bb1d5d9874d340742 100644 (file)
--- a/include/opcode/ppc.h
+++ b/include/opcode/ppc.h
@@ -59,77 +59,80 @@ extern const int powerpc_num_opcodes;
 /* Values defined for the flags field of a struct powerpc_opcode.  */
 
 /* Opcode is defined for the PowerPC architecture.  */
-#define PPC_OPCODE_PPC (01)
+#define PPC_OPCODE_PPC                  1
 
 /* Opcode is defined for the POWER (RS/6000) architecture.  */
-#define PPC_OPCODE_POWER (02)
+#define PPC_OPCODE_POWER                2
 
 /* Opcode is defined for the POWER2 (Rios 2) architecture.  */
-#define PPC_OPCODE_POWER2 (04)
+#define PPC_OPCODE_POWER2               4
 
 /* Opcode is only defined on 32 bit architectures.  */
-#define PPC_OPCODE_32 (010)
+#define PPC_OPCODE_32                   8
 
 /* Opcode is only defined on 64 bit architectures.  */
-#define PPC_OPCODE_64 (020)
+#define PPC_OPCODE_64                0x10
 
 /* Opcode is supported by the Motorola PowerPC 601 processor.  The 601
    is assumed to support all PowerPC (PPC_OPCODE_PPC) instructions,
    but it also supports many additional POWER instructions.  */
-#define PPC_OPCODE_601 (040)
+#define PPC_OPCODE_601               0x20
 
 /* Opcode is supported in both the Power and PowerPC architectures
    (ie, compiler's -mcpu=common or assembler's -mcom).  */
-#define PPC_OPCODE_COMMON (0100)
+#define PPC_OPCODE_COMMON            0x40
 
 /* Opcode is supported for any Power or PowerPC platform (this is
    for the assembler's -many option, and it eliminates duplicates).  */
-#define PPC_OPCODE_ANY (0200)
+#define PPC_OPCODE_ANY               0x80
 
 /* Opcode is supported as part of the 64-bit bridge.  */
-#define PPC_OPCODE_64_BRIDGE (0400)
+#define PPC_OPCODE_64_BRIDGE        0x100
 
 /* Opcode is supported by Altivec Vector Unit */
-#define PPC_OPCODE_ALTIVEC (01000)
+#define PPC_OPCODE_ALTIVEC          0x200
 
 /* Opcode is supported by PowerPC 403 processor.  */
-#define PPC_OPCODE_403 (02000)
+#define PPC_OPCODE_403              0x400
 
 /* Opcode is supported by PowerPC BookE processor.  */
-#define PPC_OPCODE_BOOKE (04000)
+#define PPC_OPCODE_BOOKE            0x800
 
 /* Opcode is only supported by 64-bit PowerPC BookE processor.  */
-#define PPC_OPCODE_BOOKE64 (010000)
+#define PPC_OPCODE_BOOKE64         0x1000
+
+/* Opcode is supported by PowerPC 440 processor.  */
+#define PPC_OPCODE_440             0x2000
 
 /* Opcode is only supported by Power4 architecture.  */
-#define PPC_OPCODE_POWER4 (020000)
+#define PPC_OPCODE_POWER4          0x4000
 
 /* Opcode isn't supported by Power4 architecture.  */
-#define PPC_OPCODE_NOPOWER4 (040000)
+#define PPC_OPCODE_NOPOWER4        0x8000
 
 /* Opcode is only supported by POWERPC Classic architecture.  */
-#define PPC_OPCODE_CLASSIC (0100000)
+#define PPC_OPCODE_CLASSIC        0x10000
 
 /* Opcode is only supported by e500x2 Core.  */
-#define PPC_OPCODE_SPE     (0200000)
+#define PPC_OPCODE_SPE            0x20000
 
 /* Opcode is supported by e500x2 Integer select APU.  */
-#define PPC_OPCODE_ISEL     (0400000)
+#define PPC_OPCODE_ISEL                   0x40000
 
 /* Opcode is an e500 SPE floating point instruction.  */
-#define PPC_OPCODE_EFS      (01000000)
+#define PPC_OPCODE_EFS            0x80000
 
 /* Opcode is supported by branch locking APU.  */
-#define PPC_OPCODE_BRLOCK   (02000000)
+#define PPC_OPCODE_BRLOCK        0x100000
 
 /* Opcode is supported by performance monitor APU.  */
-#define PPC_OPCODE_PMR      (04000000)
+#define PPC_OPCODE_PMR           0x200000
 
 /* Opcode is supported by cache locking APU.  */
-#define PPC_OPCODE_CACHELCK (010000000)
+#define PPC_OPCODE_CACHELCK      0x400000
 
 /* Opcode is supported by machine check APU.  */
-#define PPC_OPCODE_RFMCI    (020000000)
+#define PPC_OPCODE_RFMCI         0x800000
 
 /* A macro to extract the major opcode from an instruction.  */
 #define PPC_OP(i) (((i) >> 26) & 0x3f)