Eliminated TARGET_ALPHA, since THE_ISA provides the same function.

--HG--
extra : convert_revision : eb173a553b0782891e8b4a8e227bfb647390883a

diff --git a/arch/alpha/isa_traits.hh b/arch/alpha/isa_traits.hh
index 8781938814d06d070b5a30444222610b1b2478ec..d09b39a097d53b4e9738bae3e23c702f52001c3c 100644 (file)
--- a/arch/alpha/isa_traits.hh
+++ b/arch/alpha/isa_traits.hh
@@ -43,8 +43,6 @@ class FastCPU;
 class FullCPU;
 class Checkpoint;
 
-#define TARGET_ALPHA
-
 class StaticInst;
 class StaticInstPtr;
 

diff --git a/cpu/cpu_exec_context.hh b/cpu/cpu_exec_context.hh
index 6f725d1e48683fc578804810545375bd7f4812ba..6cc5864676055aa191f533dae4620ce480454b04 100644 (file)
--- a/cpu/cpu_exec_context.hh
+++ b/cpu/cpu_exec_context.hh
@@ -284,7 +284,7 @@ class CPUExecContext
     template <class T>
     Fault read(CpuRequestPtr &req, T &data)
     {
-#if FULL_SYSTEM && defined(TARGET_ALPHA)
+#if FULL_SYSTEM && THE_ISA == ALPHA_ISA
         if (req->flags & LOCKED) {
             req->xc->setMiscReg(TheISA::Lock_Addr_DepTag, req->paddr);
             req->xc->setMiscReg(TheISA::Lock_Flag_DepTag, true);
@@ -300,7 +300,7 @@ class CPUExecContext
     template <class T>
     Fault write(CpuRequestPtr &req, T &data)
     {
-#if FULL_SYSTEM && defined(TARGET_ALPHA)
+#if FULL_SYSTEM && THE_ISA == ALPHA_ISA
         ExecContext *xc;
 
         // If this is a store conditional, act appropriately

diff --git a/cpu/o3/alpha_cpu.hh b/cpu/o3/alpha_cpu.hh
index 0352e997277117744ed57e270f512dce2e620987..8e1e0f42a928b6e90892cbd026579a030d278eea 100644 (file)
--- a/cpu/o3/alpha_cpu.hh
+++ b/cpu/o3/alpha_cpu.hh
@@ -208,7 +208,7 @@ class AlphaFullCPU : public FullO3CPU<Impl>
     template <class T>
     Fault read(MemReqPtr &req, T &data)
     {
-#if FULL_SYSTEM && defined(TARGET_ALPHA)
+#if FULL_SYSTEM && THE_ISA == ALPHA_ISA
         if (req->flags & LOCKED) {
             req->xc->setMiscReg(TheISA::Lock_Addr_DepTag, req->paddr);
             req->xc->setMiscReg(TheISA::Lock_Flag_DepTag, true);
@@ -230,7 +230,7 @@ class AlphaFullCPU : public FullO3CPU<Impl>
     template <class T>
     Fault write(MemReqPtr &req, T &data)
     {
-#if FULL_SYSTEM && defined(TARGET_ALPHA)
+#if FULL_SYSTEM && THE_ISA == ALPHA_ISA
         ExecContext *xc;
 
         // If this is a store conditional, act appropriately

diff --git a/cpu/simple/cpu.cc b/cpu/simple/cpu.cc
index 4ac8c845c0a1bc0306c4341c983b5431680d3237..3fa84d49947a568cf20c1d807472c1a206ae03ad 100644 (file)
--- a/cpu/simple/cpu.cc
+++ b/cpu/simple/cpu.cc
@@ -941,9 +941,9 @@ SimpleCPU::tick()
 
     // maintain $r0 semantics
     cpuXC->setIntReg(ZeroReg, 0);
-#ifdef TARGET_ALPHA
+#if THE_ISA == ALPHA_ISA
     cpuXC->setFloatRegDouble(ZeroReg, 0.0);
-#endif // TARGET_ALPHA
+#endif // ALPHA_ISA
 
     if (status() == IcacheAccessComplete) {
         // We've already fetched an instruction and were stalled on an