[sim] add vector traps to vector instructions

diff --git a/riscv/insns/fld_v.h b/riscv/insns/fld_v.h
index c2d5072d1b98331f86b53fbfb8a82330786caaf7..9b4047080d551946f53486451182f7d66dfff964 100644 (file)
--- a/riscv/insns/fld_v.h
+++ b/riscv/insns/fld_v.h
@@ -1,2 +1,3 @@
+require_vector;
 require_fp;
 VEC_LOAD(FRD, load_int64, 8);

diff --git a/riscv/insns/fldst_v.h b/riscv/insns/fldst_v.h
index 60f99650ce97b04c1369badd9cb680931544e1fd..fa9b32d1c21da12150770ef942dc9b5e9d2f608f 100644 (file)
--- a/riscv/insns/fldst_v.h
+++ b/riscv/insns/fldst_v.h
@@ -1,2 +1,3 @@
+require_vector;
 require_fp;
 VEC_LOAD(FRD, load_int64, RS2);

diff --git a/riscv/insns/flw_v.h b/riscv/insns/flw_v.h
index 1e54f7e8f059a1e10d736de7b1b01a80b1ff2f17..75fdd045d4eccd7c36f8055361bea8fe1370059d 100644 (file)
--- a/riscv/insns/flw_v.h
+++ b/riscv/insns/flw_v.h
@@ -1,2 +1,3 @@
+require_vector;
 require_fp;
 VEC_LOAD(FRD, load_int32, 4);

diff --git a/riscv/insns/flwst_v.h b/riscv/insns/flwst_v.h
index d11c6324dc19317e81aaa9ebca88252b74813528..716c818ad64b5181f98d15b0ba05beabbdc8730a 100644 (file)
--- a/riscv/insns/flwst_v.h
+++ b/riscv/insns/flwst_v.h
@@ -1,2 +1,3 @@
+require_vector;
 require_fp;
 VEC_LOAD(FRD, load_int32, RS2);

diff --git a/riscv/insns/fmov_su.h b/riscv/insns/fmov_su.h
index 65d00baae7027031d59b033ab399a3805bd42901..20fa12385e2385b9234eb3af62cc271429667966 100644 (file)
--- a/riscv/insns/fmov_su.h
+++ b/riscv/insns/fmov_su.h
@@ -1,3 +1,4 @@
+require_vector;
 require_fp;
 demand(0 <= RS2 && RS2 < MAX_UTS, "ut not in range!");
 UT_FRD(RS2) = FRS1;

diff --git a/riscv/insns/fmov_sv.h b/riscv/insns/fmov_sv.h
index b689ed85aced2a0c71d693396799a3b38b2c1383..a9aa8762084056d90dbaa623f7eacfd7acf7c21c 100644 (file)
--- a/riscv/insns/fmov_sv.h
+++ b/riscv/insns/fmov_sv.h
@@ -1,3 +1,4 @@
+require_vector;
 require_fp;
 UT_LOOP_START
   UT_LOOP_FRD = FRS1;

diff --git a/riscv/insns/fmov_us.h b/riscv/insns/fmov_us.h
index 4052739620f4fb9db361dbadebc832e2a53a2f89..6f56b25054f7253e22c3ec798108bc1b6435fbb2 100644 (file)
--- a/riscv/insns/fmov_us.h
+++ b/riscv/insns/fmov_us.h
@@ -1,3 +1,4 @@
+require_vector;
 require_fp;
 demand(0 <= RS2 && RS2 < MAX_UTS, "ut not in range");
 FRD = UT_FRS1(RS2);

diff --git a/riscv/insns/fmov_vv.h b/riscv/insns/fmov_vv.h
index 28269fd0388e68855a57e86fc96b926e57b911ae..279da2186e16f8dff78e7276416a361a3653b3ab 100644 (file)
--- a/riscv/insns/fmov_vv.h
+++ b/riscv/insns/fmov_vv.h
@@ -1,3 +1,4 @@
+require_vector;
 require_fp;
 UT_LOOP_START
   UT_LOOP_FRD = UT_LOOP_FRS1;

diff --git a/riscv/insns/fsd_v.h b/riscv/insns/fsd_v.h
index 28871d54dfe3f46bc680be7347e04c75c58592bc..f619fc89266dcb1c62f590e0448cc6ec11291f1f 100644 (file)
--- a/riscv/insns/fsd_v.h
+++ b/riscv/insns/fsd_v.h
@@ -1,2 +1,3 @@
+require_vector;
 require_fp;
 VEC_STORE(FRD, store_uint64, 8);

diff --git a/riscv/insns/fsdst_v.h b/riscv/insns/fsdst_v.h
index 9a0b83d4b3bfcf861a7d90b9cfde7615b2f830a3..b3bb260b633ac89012daa2124dbab97409bd44b8 100644 (file)
--- a/riscv/insns/fsdst_v.h
+++ b/riscv/insns/fsdst_v.h
@@ -1,2 +1,3 @@
+require_vector;
 require_fp;
 VEC_STORE(FRD, store_uint64, RS2);

diff --git a/riscv/insns/fsw_v.h b/riscv/insns/fsw_v.h
index 6cb35805798ce6acb34a8e7df479baa7f0f09c27..3fe3d3f50bba3072b915c06c44e90e9746487c99 100644 (file)
--- a/riscv/insns/fsw_v.h
+++ b/riscv/insns/fsw_v.h
@@ -1,2 +1,3 @@
+require_vector;
 require_fp;
 VEC_STORE(FRD, store_uint32, 4);

diff --git a/riscv/insns/fswst_v.h b/riscv/insns/fswst_v.h
index 9991e2c3d244dca5429576b13e12f9cafae73f33..9cef9b0e44af471dd94a6cff04e93111afac9a5b 100644 (file)
--- a/riscv/insns/fswst_v.h
+++ b/riscv/insns/fswst_v.h
@@ -1,2 +1,3 @@
+require_vector;
 require_fp;
 VEC_STORE(FRD, store_uint32, RS2);

diff --git a/riscv/insns/lb_v.h b/riscv/insns/lb_v.h
index 5246d9817391761071a06578db8e398a8dc9d531..618380af199cb7913efe853bac119e5e73455482 100644 (file)
--- a/riscv/insns/lb_v.h
+++ b/riscv/insns/lb_v.h
@@ -1 +1,2 @@
+require_vector;
 VEC_LOAD(RD, load_int8, 1);

diff --git a/riscv/insns/lbst_v.h b/riscv/insns/lbst_v.h
index 91c8c3a472c6354972526507bf59ac7075f75ecb..219d90e58d1558d5b785e811eae9669ccba1edba 100644 (file)
--- a/riscv/insns/lbst_v.h
+++ b/riscv/insns/lbst_v.h
@@ -1 +1,2 @@
+require_vector;
 VEC_LOAD(RD, load_int8, RS2);

diff --git a/riscv/insns/lbu_v.h b/riscv/insns/lbu_v.h
index 72d9af2d29972c04aceef125a3a8f2c2e8abc03d..f92c8b50e03646cd8b9a016fc2ddb2c6d8b61709 100644 (file)
--- a/riscv/insns/lbu_v.h
+++ b/riscv/insns/lbu_v.h
@@ -1 +1,2 @@
+require_vector;
 VEC_LOAD(RD, load_uint8, 1);

diff --git a/riscv/insns/lbust_v.h b/riscv/insns/lbust_v.h
index 81ad75f4871521110069c2222a88c41afbea9415..09faa299a9e4709438da05150571affbf0fb34a1 100644 (file)
--- a/riscv/insns/lbust_v.h
+++ b/riscv/insns/lbust_v.h
@@ -1 +1,2 @@
+require_vector;
 VEC_LOAD(RD, load_uint8, RS2);

diff --git a/riscv/insns/ld_v.h b/riscv/insns/ld_v.h
index 124f9be154b3669b0baa91ae7d80f9ab6a8c6133..fb7a3c5cce4eba86bb36dabbb27b3fff8ee63b1d 100644 (file)
--- a/riscv/insns/ld_v.h
+++ b/riscv/insns/ld_v.h
@@ -1,2 +1,3 @@
+require_vector;
 require_xpr64;
 VEC_LOAD(RD, load_int64, 8);

diff --git a/riscv/insns/ldst_v.h b/riscv/insns/ldst_v.h
index 84aa0fc5d58eee98886055d64638c689a2ff118a..5e5de9c570f73971bfc9821c75b3605f924560d7 100644 (file)
--- a/riscv/insns/ldst_v.h
+++ b/riscv/insns/ldst_v.h
@@ -1,2 +1,3 @@
+require_vector;
 require_xpr64;
 VEC_LOAD(RD, load_int64, RS2);

diff --git a/riscv/insns/lh_v.h b/riscv/insns/lh_v.h
index 29431105e886cb06acefc48eeea1d971abe32245..269c2a8774286ce3d239aa415af2674e3cd6afc9 100644 (file)
--- a/riscv/insns/lh_v.h
+++ b/riscv/insns/lh_v.h
@@ -1 +1,2 @@
+require_vector;
 VEC_LOAD(RD, load_int16, 2);

diff --git a/riscv/insns/lhst_v.h b/riscv/insns/lhst_v.h
index 1bcd364a6a5acb350e3c071404f6f51f8d03937e..af6b5b503afbf565fbce6090c13232a571d2400a 100644 (file)
--- a/riscv/insns/lhst_v.h
+++ b/riscv/insns/lhst_v.h
@@ -1 +1,2 @@
+require_vector;
 VEC_LOAD(RD, load_int16, RS2);

diff --git a/riscv/insns/lhu_v.h b/riscv/insns/lhu_v.h
index b932aef9b520e65d16d20591da4c8d76543f75ee..7a2019dd32569b7efa6911c180c2d3885f9058cc 100644 (file)
--- a/riscv/insns/lhu_v.h
+++ b/riscv/insns/lhu_v.h
@@ -1 +1,2 @@
+require_vector;
 VEC_LOAD(RD, load_uint16, 2);

diff --git a/riscv/insns/lhust_v.h b/riscv/insns/lhust_v.h
index d1114286bca7a2aa17e7e6cf42632bda51dd0ec8..0fe845285bf18a9e7ef83d37e45d0f25a8321806 100644 (file)
--- a/riscv/insns/lhust_v.h
+++ b/riscv/insns/lhust_v.h
@@ -1 +1,2 @@
+require_vector;
 VEC_LOAD(RD, load_uint16, RS2);

diff --git a/riscv/insns/lw_v.h b/riscv/insns/lw_v.h
index 980a164e9c31a66ffb8c371f5262bc9ab005facf..6e35911bcb80be7140e666d50f731de52597dd64 100644 (file)
--- a/riscv/insns/lw_v.h
+++ b/riscv/insns/lw_v.h
@@ -1 +1,2 @@
+require_vector;
 VEC_LOAD(RD, load_int32, 4);

diff --git a/riscv/insns/lwst_v.h b/riscv/insns/lwst_v.h
index 735a6205697c672b5607158238bdf27c219f0001..5375dc030b717007d8f0d2940d1fe82d50b79793 100644 (file)
--- a/riscv/insns/lwst_v.h
+++ b/riscv/insns/lwst_v.h
@@ -1 +1,2 @@
+require_vector;
 VEC_LOAD(RD, load_int32, RS2);

diff --git a/riscv/insns/lwu_v.h b/riscv/insns/lwu_v.h
index b1cdf3796675b20f8658845dc6ae548706dc7e1d..4fa1489ffe292ae82aa83bb576a08e7e4fc62e1f 100644 (file)
--- a/riscv/insns/lwu_v.h
+++ b/riscv/insns/lwu_v.h
@@ -1 +1,2 @@
+require_vector;
 VEC_LOAD(RD, load_uint32, 4);

diff --git a/riscv/insns/lwust_v.h b/riscv/insns/lwust_v.h
index 7e0c006248ae39a136e78f4fe4184107f40e3c08..328e23f604bf4bb159774ca12155c8a04612d853 100644 (file)
--- a/riscv/insns/lwust_v.h
+++ b/riscv/insns/lwust_v.h
@@ -1 +1,2 @@
+require_vector;
 VEC_LOAD(RD, load_uint32, RS2);

diff --git a/riscv/insns/mov_su.h b/riscv/insns/mov_su.h
index b55ab2f69f591a3e5499e0bc89e8967a200115cc..7b7cae14719c7bc57246d731b1cb7cbc7004692d 100644 (file)
--- a/riscv/insns/mov_su.h
+++ b/riscv/insns/mov_su.h
@@ -1,2 +1,3 @@
+require_vector;
 demand(0 <= RS2 && RS2 < MAX_UTS, "ut not in range!");
 UT_RD(RS2) = RS1;

diff --git a/riscv/insns/mov_sv.h b/riscv/insns/mov_sv.h
index 03bb29df3a1a436cbfa789c54d487ad41e5bf11f..c6f4c2c89e9dbb3c97947a5ae3e35040072cd233 100644 (file)
--- a/riscv/insns/mov_sv.h
+++ b/riscv/insns/mov_sv.h
@@ -1,3 +1,4 @@
+require_vector;
 UT_LOOP_START
   UT_LOOP_RD = RS1;
 UT_LOOP_END

diff --git a/riscv/insns/mov_us.h b/riscv/insns/mov_us.h
index 05699a8d19698de0973876e6c29622489814bc95..a69e3888328d2bdf407224448069e7931caf1cda 100644 (file)
--- a/riscv/insns/mov_us.h
+++ b/riscv/insns/mov_us.h
@@ -1,2 +1,3 @@
+require_vector;
 demand(0 <= RS2 && RS2 < MAX_UTS, "ut not in range");
 RD = UT_RS1(RS2);

diff --git a/riscv/insns/mov_vv.h b/riscv/insns/mov_vv.h
index 2a1b0b6c32584eb266ef359beb9a82d092acad40..91d63d400c9bace8551837cb655148b01bcabadc 100644 (file)
--- a/riscv/insns/mov_vv.h
+++ b/riscv/insns/mov_vv.h
@@ -1,3 +1,4 @@
+require_vector;
 UT_LOOP_START
   UT_LOOP_RD = UT_LOOP_RS1;
 UT_LOOP_END

diff --git a/riscv/insns/sb_v.h b/riscv/insns/sb_v.h
index 81e35130693000bf0ed4cb7a923d187d7c549dfd..c3d5b9d7ba5fc4e41adf025a35855e0e7d5e05ca 100644 (file)
--- a/riscv/insns/sb_v.h
+++ b/riscv/insns/sb_v.h
@@ -1 +1,2 @@
+require_vector;
 VEC_STORE(RD, store_uint8, 1);

diff --git a/riscv/insns/sbst_v.h b/riscv/insns/sbst_v.h
index 2d7c59bca1c77f936c3e33e7309d574cb9f3794e..b83cc50f3bf3c428eb3d28f1474105c15e8ffa78 100644 (file)
--- a/riscv/insns/sbst_v.h
+++ b/riscv/insns/sbst_v.h
@@ -1 +1,2 @@
+require_vector;
 VEC_STORE(RD, store_uint8, RS2);

diff --git a/riscv/insns/sd_v.h b/riscv/insns/sd_v.h
index 330e1b0017f13945024903017f3815c47baf3ae4..9c02069621ca5b55a104859144bfcc8738d11f2f 100644 (file)
--- a/riscv/insns/sd_v.h
+++ b/riscv/insns/sd_v.h
@@ -1,2 +1,3 @@
+require_vector;
 require_xpr64;
 VEC_STORE(RD, store_uint64, 8);

diff --git a/riscv/insns/sdst_v.h b/riscv/insns/sdst_v.h
index d3e74d32b96df8bbd400dc2524f77b25bfaa9f68..26868d23baafa57a2d4b404991e2687dd62d92c2 100644 (file)
--- a/riscv/insns/sdst_v.h
+++ b/riscv/insns/sdst_v.h
@@ -1,2 +1,3 @@
+require_vector;
 require_xpr64;
 VEC_STORE(RD, store_uint64, RS2);

diff --git a/riscv/insns/setvl.h b/riscv/insns/setvl.h
index 5b611db0633324129645aa9971c1811a8316b18d..c2212ff5ebd427735f6c0d125e73be6d664e4237 100644 (file)
--- a/riscv/insns/setvl.h
+++ b/riscv/insns/setvl.h
@@ -1,2 +1,3 @@
+require_vector;
 setvl(RS1);
 RD = VL;

diff --git a/riscv/insns/sh_v.h b/riscv/insns/sh_v.h
index fdfe6fe3d82ea957a275e790da472dc0fa608f83..623eda82c57624317f74ffcf39f6474c94cdfc9d 100644 (file)
--- a/riscv/insns/sh_v.h
+++ b/riscv/insns/sh_v.h
@@ -1 +1,2 @@
+require_vector;
 VEC_STORE(RD, store_uint16, 2);

diff --git a/riscv/insns/shst_v.h b/riscv/insns/shst_v.h
index 4f4044ce073f7107389aa787fb777591d232ed98..3904331cb71349567330245dac5b9dff4032742a 100644 (file)
--- a/riscv/insns/shst_v.h
+++ b/riscv/insns/shst_v.h
@@ -1 +1,2 @@
+require_vector;
 VEC_STORE(RD, store_uint16, RS2);

diff --git a/riscv/insns/stop.h b/riscv/insns/stop.h
index cbf69dc2bae97aebcb15ea6073cb4206e3bc1c51..791a82cbcf86f969aae9c0de80aaf0010b80d536 100644 (file)
--- a/riscv/insns/stop.h
+++ b/riscv/insns/stop.h
@@ -1,2 +1,3 @@
+require_vector;
 utmode = false;
 throw vt_command_stop;

diff --git a/riscv/insns/sw_v.h b/riscv/insns/sw_v.h
index 276da954f7a8f2258e33857c1cf1f8530bd2c7f2..662d4e33fe173b15fdf5264543285d1d7008c8b8 100644 (file)
--- a/riscv/insns/sw_v.h
+++ b/riscv/insns/sw_v.h
@@ -1 +1,2 @@
+require_vector;
 VEC_STORE(RD, store_uint32, 4);

diff --git a/riscv/insns/swst_v.h b/riscv/insns/swst_v.h
index 08b198cef73bdda0bf48a061c7fbc91351894406..8f0595330f8e123defe18bd672ba429db0eb858c 100644 (file)
--- a/riscv/insns/swst_v.h
+++ b/riscv/insns/swst_v.h
@@ -1 +1,2 @@
+require_vector;
 VEC_STORE(RD, store_uint32, RS2);

diff --git a/riscv/insns/utidx.h b/riscv/insns/utidx.h
index 70336acd0f04c7bcd7e3ae5d2036093222534d00..b3c944cf16d3f335d84b9f1e50097a847ef4172c 100644 (file)
--- a/riscv/insns/utidx.h
+++ b/riscv/insns/utidx.h
@@ -1 +1,2 @@
+require_vector;
 RD = utidx;

diff --git a/riscv/insns/vcfgivl.h b/riscv/insns/vcfgivl.h
index c870f673121da78ac9f1986ee8ba387a29c2ed9c..0ded9f86d26f9720c1bb068911193808c2f7dfc2 100644 (file)
--- a/riscv/insns/vcfgivl.h
+++ b/riscv/insns/vcfgivl.h
@@ -1,3 +1,4 @@
+require_vector;
 nxpr_use = SIMM & 0x3f;
 nfpr_use = (SIMM >> 6) & 0x3f;
 vcfg();

diff --git a/riscv/insns/vf.h b/riscv/insns/vf.h
index eff542cf0f14d0a17fffc09ce0faa993a033a607..c3a43cf4b627510267e9303fbef1c46821b3180b 100644 (file)
--- a/riscv/insns/vf.h
+++ b/riscv/insns/vf.h
@@ -1,3 +1,4 @@
+require_vector;
 for (int i=0; i<VL; i++)
 {
   uts[i]->pc = RS1+SIMM;

diff --git a/riscv/trap.h b/riscv/trap.h
index a5c32125fcbe130d80ba6df8f79736fb1b0f13ea..8424d80b9e66182feb59f9c25a656dc94e753396 100644 (file)
--- a/riscv/trap.h
+++ b/riscv/trap.h
@@ -13,7 +13,7 @@
   DECLARE_TRAP(data_address_misaligned), \
   DECLARE_TRAP(load_access_fault), \
   DECLARE_TRAP(store_access_fault), \
-  DECLARE_TRAP(trap_vector_disabled), \
+  DECLARE_TRAP(vector_disabled), \
   DECLARE_TRAP(reserved2), \
   DECLARE_TRAP(reserved3), \
   DECLARE_TRAP(reserved4), \